JPH0156473B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a delayed discharge circuit that quickly lowers the word line potential of a static type memory upon transition to non-selection.

Technology background In memory ICs that use saturated cells, such as PNP memory ICs and I ₂ L memory ICs, it is important to quickly lower the potential of a selected word line when making it non-selected in order to prevent multiple selections. be. For this purpose, a discharge circuit is provided for the word line, but this circuit continues to discharge the selected word line for a certain period of time (generally 5 to 10 nsec) even after the output of the word line driver that drives (selects) the word line switches to the non-select level. It is necessary to be a delay type that continues to discharge the charge on the line.

Conventional technology and problems In conventional delayed discharge circuits, the discharge time constant (delay time) is generally determined by a capacitor and a resistor. This has the disadvantage that the entire circuit occupies a large area.

OBJECTS OF THE INVENTION The present invention uses elements of PNP structure in the discharge circuit for each word line to enable delayed discharge and to reduce the overall occupied area.

Structure of the Invention The present invention provides a delayed discharge circuit that is connected to a word line pair to which a static memory cell is connected, and forcibly lowers the potential of the word line when the word line pair is transitioned from selection to non-selection. A PNP transistor whose emitter is connected to the high potential side word line via a level shift element, a base and a first collector connected to the collector and base of the PNP transistor, respectively, and a second collector or second emitter. is characterized in that it comprises an NPN transistor connected to the word line on the low potential side, and a constant current source or constant voltage source connected to the emitter of the NPN transistor to cause the word line discharge current to flow through the transistor. This will be explained in detail below with reference to the drawings.

Embodiment of the Invention Figure 1a shows the basic configuration of the delayed discharge circuit of the present invention, _Q1 is a PNP transistor whose emitter is connected to the positive side (high potential side) word line W, and _Q2 is a PNP transistor whose one collector is connected to the word line W. A multi-collector type NPN transistor connected to a word line C on the negative side (low potential side) that is paired with the word line W, 1 is a transistor Q ₂
It is a constant current source that causes current I to flow through the emitter of.
The collector of transistor Q ₁ and the base of transistor Q ₂ (both P type) are connected in common, and the base of transistor Q ₁ and the remaining collector of transistor Q ₂ (both N type) are connected in common. , the element structure is PNPN like a thyristor.
becomes. Figure b shows this, where 2 is the emitter of transistor _Q1 , 3 is the base of the same transistor and the collector of transistor _Q2 , and 4 is the collector of transistor _Q1 and the transistor
The base of _Q2 , 5 is the emitter of transistor _Q2 . Although the thyristor does not turn on unless triggered, the DC characteristics of the thyristor formed by an integrated circuit are equivalent to the diode 6 shown in FIG. 1c. Because when current is flowing,
This is because both PNP transistor Q ₁ and NPN transistor Q ₂ are saturated and all three junctions are forward biased. Note that in order to obtain current-voltage characteristics equivalent to those of the diode 6, the parameters of the two transistors Q ₁ and Q ₂ must be controlled to appropriate values, but this is very easy. The present invention utilizes this saturation characteristic. As is generally known, the collector-emitter junction capacitance of a saturated transistor becomes very large due to the diffusion capacitance component, and there is a large amount of accumulated charge. This means that conventional capacitors can be made smaller. The present invention also takes advantage of this point.

FIG. ₂ is a diagram showing an embodiment of the present invention.
7 _o is a delayed discharge circuit (element) provided for each word line, WD ₁ to WD _o are word line drivers, MC ₁
~MC _o is a saturated memory cell. Discharge circuit 7 ₁
~7 _o PNP transistor Q ₁₁ ~Q _1o is Q ₁ in Fig. 1
and the NPN transistor Q ₂₁ ~Q _2o is equivalent to Q ₂
corresponds to A constant current source 1 is provided in common, and the emitters of transistors Q ₂₁ to _{Q 2o} are commonly connected (constituting a current switch). R ₁ -R _o are level shift or voltage drop resistors inserted between the word lines W ₁ -W _o and the emitters of the transistors Q ₁₁ -Q _1o . Memory cell MC (MC ₁ , MC ₂
. . . (hereinafter the same) takes the configuration shown in FIG. 3, for example. In the figure, Q ₃ and Q ₄ are PNP transistors serving as loads, Q ₅ and Q ₆ are NPN transistors (multi-emitter) for driving, and B is a bit line pair.

Now, selection signal _X1 is at high potential (for example -0.9V)
Assume that the word line _W1 is selected and the other selection signals (Xn is one of them) are in a non-selected state at a low potential (for example, -1.9V). The current I of the constant current source 1 flows only through the discharge circuit ₇₁ connected to the word line _W1 having the highest potential. That is, when the potential of the word line _W1 is high, a current first flows between the emitter and the base of the transistor _Q11 , which becomes the base current of the transistor, and the collector current flows. This collector current becomes the base current of transistor _Q21 ,
The base current of _Q11 becomes the collector current of _Q21 , turning on transistor _Q21 . This turns on the PNPN structure from the emitter of transistor _Q11 to the emitter of transistor _Q21 . At this time, transistors Q ₁₁ and Q ₂₁ are deeply saturated,
The base potential of Q ₂₁ is approximately equal to the emitter potential of Q ₁₁ (the same potential is shown in the figure). Also
Since Q ₂₁ is a multi-collector transistor,
A certain percentage of the current (I) drawn (e.g. 80
%) flows from the second collector. For example, R
= 1.5KΩ, 0.4m from the emitter of _Q11
A. It will flow. Incidentally, at this time, the discharge circuit (for example, 7 _o ) connected to the non-selected row is also in the on state. In other words, since the discharge circuit 7 _o is connected to the word line with a low potential, no discharge current flows.
The emitter potential of Q _1o is approximately equal to the potential of W _o (-1.9V). Further, the potential of the second collector of Q _2o is equal to the potential of _Co (−2.7V). Therefore, the second collector of Q _2o acts as an emitter and collects from the emitter of Q _1o .
PNPN leading to the second collector of Q _2o will be turned on. However, the PNPN structure of the path from the emitter of Q _1o to the emitter of Q _2o is off. Let us now consider a case where the potential of the base (X ₁ ) of the driver transistor WD ₁ in the selected column W ₁ is switched from the selected potential (−0.1 V) to the non-selected potential (−1.1 V).

FIG. 4 is a conceptual diagram showing fluctuations in word line potential and discharge current. Transistor as mentioned above
Since Q ₁₁ and Q ₂₁ are saturated and there is a delay in fluctuation of the base potential, the discharge current I continues to flow for a certain delay time. In this way, even after the word line _W1 becomes non-selected, the discharge continues, and the word lines W,
C. The remaining charge accumulated in the memory cell portion is forcibly removed, the word line drops steeply, and two-electrode selection is blocked. Also, resistors R ₁ to _{R o} serve to lower the level of the discharge circuit leading to the selected row. Without this, the second collector of Q ₂₁ would be fully forward biased and the discharge current would be mainly W ₁ , Q ₁₁
The cell discharge current will flow through this path and the cell discharge current will disappear.

In FIG. 5, the resistors R ₁ to _{R o} in FIG. 4 are replaced with diodes D ₁ to _{D o} . This is an embodiment modified by focusing on the point that a resistor is necessary for level shifting. However, in this case, PNPN is completely turned off when not selected.

Figure 6 shows that the basic circuit in Figure 1 uses a multi-collector NPN-Tr, whereas the basic circuit uses a multi-emitter NPN-Tr.
This is an example using NPN-Tr. In this case, when selected, the second emitter operates in reverse and acts as a collector. Furthermore, by changing the current amplification factors of the two emitters, the current drawn from the negative word line can be controlled. In this case, the operating principle of the circuit is the same as the circuit of FIG. Note that in either example, the constant current source 1 may be a constant voltage source.

Effects of the Invention As described above, according to the present invention, there is no need to use a capacitor or a high resistance, so the area occupied by the delayed discharge circuit can be small. Furthermore, when used in a PNPN memory with the equivalent circuit shown in FIG. 6, it has the same structure as a memory cell, so manufacturing is simple, and there is also the advantage that the time constant changes automatically according to the memory cell capacity.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing the basic configuration of the present invention, Figure 2 is an explanatory diagram showing the basic configuration of the present invention.
3 is a circuit diagram showing an example of a saturated memory cell, FIG. 4 is a waveform diagram showing delayed discharge characteristics, and FIG. 5 is a diagram showing another embodiment of the invention. FIG. 6 is a block diagram showing another embodiment of the present invention. In the figure, W ₁ to _{W o} are positive word lines, C ₁ to _Co are negative word lines, MC ₁ to MC o are memory cells, and Q ₁₁ to _{MC o} are memory cells.
Q _1o is a PNP transistor, Q ₂₁ to _{Q 2o} are NPN transistors, R ₁ to _Ro and D ₁ to D _o are level shift elements, 1 is a constant current source, and 7 ₁ to 7 _o are delayed discharge circuit elements. be.

Claims (1)

[Claims] 1 A delayed discharge circuit that is connected to a word line pair to which a static memory cell is connected, and forcibly lowers the potential of the word line when the word line pair is transitioned from selection to non-selection, and is connected to the high potential side. A PNP transistor whose emitter is connected to the word line via a level shift element, a base and a first transistor connected to the collector and base of the PNP transistor, respectively.
NPN whose collector is connected and the second collector or second emitter is connected to the low potential side word line.
1. A word line delayed discharge circuit comprising a transistor, and a constant current source or constant voltage source connected to the emitter of the NPN transistor to cause a word line discharge current to flow through the transistor.