JPH0156480B2 - - Google Patents
Info
- Publication number
- JPH0156480B2 JPH0156480B2 JP58203986A JP20398683A JPH0156480B2 JP H0156480 B2 JPH0156480 B2 JP H0156480B2 JP 58203986 A JP58203986 A JP 58203986A JP 20398683 A JP20398683 A JP 20398683A JP H0156480 B2 JPH0156480 B2 JP H0156480B2
- Authority
- JP
- Japan
- Prior art keywords
- information
- signal
- comparison
- address
- rom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は読み出し専用メモリ（以後ROMと称
す）を含むデータ処理装置に関し、とくにシング
ルチツプマイクロコンピユータと呼ばれ中央処理
装置、入出力装置及びメモリが単一半導体チツプ
上に集積化されたものに関する。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a data processing device including a read-only memory (hereinafter referred to as ROM), and in particular, to a data processing device called a single-chip microcomputer, which includes a central processing unit, an input/output device, and a memory. integrated on a single semiconductor chip.
シングルチツプマイクロコンピユータでは半導
体集積回路の製造過程において利用者に専用化さ
れたプログラムがチツプ上のメモリ（ROM）に
書き込まれる。そしてこのROMに書き込まれた
記憶情報のチエツクは集積回路チツプの外部より
ROMのアドレス情報を入力してアクセスされた
ROM情報をチツプ外部に出力させて行なつてい
た。従つて、アドレスを印加するだけで何人にも
容易にROM情報がわかるため、プログラム情報
の機密保持の面で大きな問題があつた。
In a single-chip microcomputer, a user-specific program is written into the memory (ROM) on the chip during the manufacturing process of semiconductor integrated circuits. The memory information written in this ROM can be checked from outside the integrated circuit chip.
Accessed by entering ROM address information
This was done by outputting ROM information outside the chip. Therefore, anyone can easily know the ROM information just by applying an address, which poses a major problem in terms of maintaining the confidentiality of program information.
本発明は第３者にプログラム内容が知れること
なくそのチエツクができるようにした情報処理装
置を提供することである。
An object of the present invention is to provide an information processing device that allows a third party to check the program contents without knowing the contents.
シングルチツプマイクロコンピユータは内部で
ROMプログラムを実行し外部に対してこれを出
力する必要が無いことに着目し、本発明はプログ
ラムを知つた者が外部から情報を入力し、これと
ROMの内容とをチツプ上で比較判定する手段を
設けたことを特徴とする。
A single-chip microcomputer internally
Focusing on the fact that there is no need to execute a ROM program and output it to the outside, the present invention allows a person who knows the program to input information from the outside and use it.
It is characterized by providing means for comparing and determining the contents of the ROM on the chip.
本発明によれば、ROM内容をチツプ外に出力
することなくチツプ上ででこれをチエツクできる
ため、第３者に対する機密保護は万全である。し
かし、内容をみてチエツクせずとも、比較結果だ
けでよいので内容チエツク作業も非常に簡単でよ
い。
According to the present invention, the contents of the ROM can be checked on the chip without being output to the outside of the chip, so that security against third parties is completely ensured. However, the task of checking the contents is very simple because only the comparison results are needed without checking the contents.
第１図は本発明の一実施例のデータ処理装置の
構成を示すブロツク線図である。第１図におい
て、１００はデータ処理装置、１０１はROM、
１０２はアドレス指定部、１０３は比較部、１０
４は判定部、１０５〜１１１は信号及び情報の転
送線を示す。信号１０５はアドレス指定開始信
号、信号１０６はアドレス指定終了信号、情報１
０７はアドレス指定情報、情報１０８はROM記
憶情報、情報１０９は比較入力情報、信号１１０
は比較結果信号、信号１１１は判定終了信号を示
す。アドレス指定部１０２はROM１０１のアド
レス情報１０７、アドレス指定終了信号１０６を
発生する。比較部１０３はROM１０１の記憶情
報１０８と比較入力情報１０９とを比較し結果信
号１１０を出力する。判定部１０４はアドレス指
定開始信号１０５とアドレス指定終了信号１０６
と比較結果信号１１０に基づき判定終了信号１１
１を出力する。
FIG. 1 is a block diagram showing the configuration of a data processing device according to an embodiment of the present invention. In FIG. 1, 100 is a data processing device, 101 is a ROM,
102 is an address designation section, 103 is a comparison section, 10
Reference numeral 4 indicates a determination unit, and reference numerals 105 to 111 indicate signal and information transfer lines. Signal 105 is an addressing start signal, signal 106 is an addressing end signal, information 1
07 is address designation information, information 108 is ROM storage information, information 109 is comparison input information, signal 110
indicates a comparison result signal, and signal 111 indicates a determination end signal. The address designation unit 102 generates address information 107 of the ROM 101 and an address designation end signal 106. Comparison unit 103 compares storage information 108 of ROM 101 and comparison input information 109 and outputs a result signal 110. The determination unit 104 receives an addressing start signal 105 and an addressing end signal 106.
Judgment end signal 11 based on the comparison result signal 110
Outputs 1.
以下、本回路の動作を説明する。アドレス指定
開始信号１０５が発生するときアドレス指定部１
０２に開始アドレス値を設定し判定部１０４に判
定結果一致に対応する状態を設定しアドレス指定
情報１０７を介してROM１０１をアドレス指定
する。ROM１０１は前記アドレスの記憶情報を
情報転送線１０８を介し比較部１０３に転送す
る。他方データ処理装置１００の外部より入力し
た比較入力情報１０９は比較部１０３に入力さ
れ、前記ROM１０１からの記憶情報１０８と比
較され、一致しない場合に比較部１０３は比較結
果信号１１０を発生し判定手段１０４へ伝える。
ここでアドレス指定部１０２はアドレス情報を順
次更新し、前記更新に同期して入力する比較情報
１０９を変化させ比較部１０３にて連続的に比較
する。判定部１０４は前記比較結果信号１１０が
発生するとき判定結果不一致に対応する状態に変
化し、アドレス指定部１０２からのアドレス指定
終了信号１０６が発生するとき前記判定結果の状
態を判定終了信号１１１として出力する。 The operation of this circuit will be explained below. When the addressing start signal 105 is generated, the addressing section 1
A start address value is set in 02, a state corresponding to a match in the judgment result is set in the judgment unit 104, and the ROM 101 is addressed via the addressing information 107. The ROM 101 transfers the storage information of the address to the comparison unit 103 via the information transfer line 108. On the other hand, the comparison input information 109 inputted from outside the data processing device 100 is inputted to the comparison section 103 and compared with the storage information 108 from the ROM 101. If they do not match, the comparison section 103 generates a comparison result signal 110, and the comparison section 103 generates a comparison result signal 110. Report to 104.
Here, the address specifying unit 102 sequentially updates the address information, changes the comparison information 109 inputted in synchronization with the update, and continuously compares the information in the comparing unit 103. When the comparison result signal 110 is generated, the determination unit 104 changes to a state corresponding to the determination result mismatch, and when the address designation end signal 106 from the address designation unit 102 is generated, the determination unit 104 changes the state of the determination result as the determination end signal 111. Output.
つまり、第１図実施例のデータ処理装置では、
外部から比較情報をアドレス指定開始信号とを入
力し、データ処理装置内部でアドレス指定情報を
更新し、前記比較入力情報とアドレス指定に基く
ROM記憶情報とを連続的に比較しアドレス指定
終了番地まで一致がとれた場合に一致判定の信号
が出力される。 In other words, in the data processing device of the embodiment shown in FIG.
Input the comparison information and the addressing start signal from the outside, update the addressing information inside the data processing device, and based on the comparison input information and the addressing.
The information stored in the ROM is continuously compared with the information stored in the ROM, and if a match is found up to the end address of the address specification, a match determination signal is output.
第１図の実施例の比較部１０３と判定部１０４
について回路構成を示して説明する。第２図は比
較部１０３の論理回路図づ２００〜２０７は比較
回路、２０８は比較出力回路、情報A0〜7は
ROMからの記憶情報、情報B0〜7は比較入力情
報、信号２０９は比較結果出力を示す。比較回路
２００〜２０７は各々情報A0〜7と情報B0〜7を
入力としてその排他的論理和信号を出力する。比
較出力回路２０８は比較回路２００〜２０７から
出力される信号の論理和をとる。本比較部は
ROMの記憶情報A0〜7と比較入力情報B0〜7とを
比較回路２００〜２０７により排他的論理和をと
り、結果が不一致のときつまりいずれかの比較回
路出力が“１”の場合には比較出力回路２０８で
論理和がとられ、比較結果信号２０９が“１”と
なり、比較回路２００〜２０７全てにおいて比較
情報が一致している場合には比較結果信号２０９
が“０”となる。ゆえにROM記憶情報と外部よ
り入力した比較入力情報とを比較することにより
不一致の場合にはその意を示す信号２０９を判定
部に出力する機能を有する。第３図は判定部１０
４の論理回路で３０１は判定回路、３０２，３０
３は判定終了回路、３０４〜３０８は信号または
転送線を示す。信号３０５はアドレス指定開始信
号、信号３０６は比較結果信号、信号３０４はア
ドレス指定終了信号、信号３０７は判定終了信
号、信号３０８は判定終了不一致信号であり、判
定回路３０１はアドレス指定開始信号３０５と比
較結果信号３０６を基に判定状態を記憶するセツ
トリセツトフリツプフロツプ（以後RS―Ｆ／Ｆ
と称す）、判定終了回路３０２，３０３はアドレ
ス指定終了情報３０４と判定回路３０１の出力を
基に各々判定終了信号３０７と判定終了不一致信
号３０８を出力する。第３図の判定部ではアドレ
ス指定開始信号３０５が発生するとき判定回路３
０１のRS―Ｆ／Ｆがセツトされ、比較結果信号
３０６が発生することなく順次アドレスと比較情
報を更新しアドレス指定終了となつたときアドレ
ス指定終了信号３０４が発生し前記RS―Ｆ／Ｆ
の出力Ｑが“１”、つまりアドレス終了番地まで
ROMの情報と比較情報が一致しているならば判
定終了回路３０２の論理積出力が“１”となり判
定終了信号３０７を出力する。他方比較情報と
ROMの情報が不一致の場合、比較部から比較結
果信号３０６が発生され、判定回路３０１のRS
―Ｆ／Ｆがリセツトされ、出力が“１”、出力
Ｑが“０”となるため判定終了回路３０３の論理
積が“１”となり判定終了不一致信号３０８を出
力する。尚、第１図実施例のアドレス指定部１０
２はROM１０１のアドレス情報を発生するため
のカウンタであり一定の時間毎に発生するアドレ
ス値を更新する。ここでカウンタをアドレス指定
終了番地からカウントアツプするとオーバーフロ
ー信号が発生されるため、該オーバーフロー信号
をアドレス指定終了信号３０４として判定終了回
路３０２，３０３へ入力している。実施例では記
憶情報判定を開始してROM情報と入力する比較
情報が一致しなければ判定の途中で前記判定回路
３０１のRS―Ｆ／Ｆがリセツトされた状態でア
ドレス指定終了番地まで比較を続けすべての比較
が終了した時点ではじめて判定結果を判定終了信
号として出力する。ゆえにデータ処理装置の
ROM情報を知る者にとつては順次比較すべき情
報を入力するだけで目的とする情報が正しく
ROMに記憶されているか否かを容易に判定でき
る。しかしROM情報を知らない者が記憶情報を
知ろうとする場合には入力する比較情報とそのシ
ーケンス全てについて試みる必要があり、その読
み出しのために多大な時間を要するから、本実施
例は機密保護手段としては優秀である。 Comparison unit 103 and determination unit 104 in the embodiment shown in FIG.
The circuit configuration will be shown and explained. FIG. 2 is a logic circuit diagram of the comparator 103. 200 to 207 are comparison circuits, 208 is a comparison output circuit, and information A 0 to 7 are
Storage information from the ROM, information B 0 to 7 indicates comparison input information, and signal 209 indicates comparison result output. Comparing circuits 200-207 each receive information A 0 - 7 and information B 0 - 7 as inputs and output their exclusive OR signals. Comparison output circuit 208 takes the logical sum of the signals output from comparison circuits 200-207. This comparison section is
The ROM storage information A 0 to 7 and the comparison input information B 0 to 7 are exclusive ORed by comparison circuits 200 to 207, and when the results do not match, that is, when any of the comparison circuit outputs is "1", are ORed in the comparison output circuit 208, and the comparison result signal 209 becomes "1". If the comparison information matches in all the comparison circuits 200 to 207, the comparison result signal 209
becomes “0”. Therefore, it has a function of comparing the ROM storage information and the comparison input information input from the outside and outputting a signal 209 indicating this to the determination section if they do not match. FIG. 3 shows the determination unit 10
4 logic circuit, 301 is a judgment circuit, 302, 30
3 indicates a determination end circuit, and 304 to 308 indicate signal or transfer lines. The signal 305 is an addressing start signal, the signal 306 is a comparison result signal, the signal 304 is an addressing end signal, the signal 307 is a judgment end signal, and the signal 308 is a judgment end mismatch signal. A reset flip-flop (hereinafter referred to as RS-F/F) that stores the judgment state based on the comparison result signal 306
The determination end circuits 302 and 303 output a determination end signal 307 and a determination end mismatch signal 308, respectively, based on the addressing end information 304 and the output of the determination circuit 301. In the determination section of FIG. 3, when the addressing start signal 305 is generated, the determination circuit 3
RS-F/F 01 is set, and the address and comparison information are sequentially updated without generating the comparison result signal 306. When the address designation is completed, the address designation end signal 304 is generated and the RS-F/F
output Q is “1”, that is, up to the end address
If the information in the ROM and the comparison information match, the AND output of the judgment end circuit 302 becomes "1" and a judgment end signal 307 is output. On the other hand, with comparative information
If the information in the ROM does not match, the comparison section generates a comparison result signal 306, and the RS of the determination circuit 301
- Since the F/F is reset and the output becomes "1" and the output Q becomes "0", the AND of the judgment end circuit 303 becomes "1" and the judgment end mismatch signal 308 is output. Note that the address designation unit 10 of the embodiment in FIG.
2 is a counter for generating address information of the ROM 101, and updates the address value generated at regular intervals. Here, when the counter is counted up from the address specification end address, an overflow signal is generated, so the overflow signal is inputted as the address specification end signal 304 to the judgment end circuits 302 and 303. In the embodiment, storage information judgment is started, and if the ROM information and the input comparison information do not match, the RS-F/F of the judgment circuit 301 is reset during the judgment and the comparison is continued until the end address of the address specification. Only when all comparisons are completed, the determination result is output as a determination end signal. Therefore, the data processing equipment
For those who know ROM information, simply inputting the information to be compared sequentially will ensure that the desired information is correct.
It can be easily determined whether the data is stored in the ROM or not. However, if a person who does not know the ROM information tries to know the stored information, it is necessary to try all the input comparison information and its sequence, and it takes a lot of time to read it. Therefore, this embodiment is a security protection method. It is excellent.
例えばROM内容の一語が８ビツトであるとす
ると一語は256個の情報をもつことができる。
ROM容量が８語で一語の読み出し時間に10μ秒
必要とするならばROMの情報を解読するまでに
必要とする時間は2568×10×10-6秒であり、年間
に換算すると約58万年となる。ここでデータ処理
装置に内蔵されるROM容量は1000語以上であ
り、その記憶情報を知らない者が記憶情報を知ろ
うとすることは実際には不可能である。 For example, if one word of ROM content is 8 bits, one word can contain 256 pieces of information.
If the ROM capacity is 8 words and it takes 10 microseconds to read one word, the time required to decode the ROM information is 256 8 × 10 × 10 -6 seconds, which is approximately 58 seconds per year. It will last a million years. Here, the ROM capacity built into the data processing device is 1000 words or more, and it is actually impossible for someone who does not know the stored information to try to know the stored information.
以上本発明によればデータ処理装置のROM記
憶情報を外部に出力することなく正しくROMに
情報が記憶されていることを判定でき、記憶情報
を読み出しにくい、つまりROM内容の盗用が容
易でない効果が得られ、機密保持機能の向上を計
ることができる。 As described above, according to the present invention, it is possible to determine whether information is correctly stored in the ROM without outputting the ROM storage information of the data processing device to the outside, and there is an effect that it is difficult to read the stored information, that is, it is difficult to steal the ROM contents. It is possible to improve the confidentiality function.
第１図は本発明の一実施例のブロツク構成図、
第２図は第１図の実施例の比較部の回路構成図、
第３図は第１図の実施例の判定部の回路構成図で
ある。
１００……データ処理装置、１０１……
ROM、１０２……アドレス指定部、１０３……
比較部、１０４……判定部、１０５……アドレス
指定開始信号、１０６……アドレス指定終了信
号、１０７……アドレス情報、１０８……ROM
記憶情報、１０９……比較入力情報、１１０……
比較結果信号、１１１……判定終了信号、２００
〜２０７……比較回路、A0〜7……ROM記憶情
報、２０８……比較出力信号、B0〜7……比較入
力情報、２０９……比較結果信号、３０１……判
定回路、３０２，３０３……判定終了回路、３０
４……アドレス指定終了信号、３０５……アドレ
ス指定開始信号、３０６……比較結果信号、３０
７……判定終了信号、３０８……判定終了不一致
信号。
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a circuit configuration diagram of the comparison section of the embodiment shown in FIG.
FIG. 3 is a circuit diagram of the determination section of the embodiment shown in FIG. 1. 100...data processing device, 101...
ROM, 102...Address specification section, 103...
Comparison unit, 104...Determination unit, 105...Address specification start signal, 106...Address specification end signal, 107...Address information, 108...ROM
Memory information, 109... Comparison input information, 110...
Comparison result signal, 111...Judgment end signal, 200
~207... Comparison circuit, A 0 - 7 ... ROM storage information, 208... Comparison output signal, B 0 - 7 ... Comparison input information, 209... Comparison result signal, 301... Judgment circuit, 302, 303 ...Judgment end circuit, 30
4... Address specification end signal, 305... Address specification start signal, 306... Comparison result signal, 30
7... Judgment end signal, 308... Judgment end mismatch signal.
Claims (1)
報処理装置において、前記読み出し専用メモリの
アドレス指定情報を発生するアドレス指定部と、
前記アドレスの読み出し専用メモリの記憶データ
とチツプの外部から入力されるデータとを比較す
る比較部を備え、アドレス指定部で順次アドレス
を更新すると共に入力データとの比較を行い、そ
の一致または不一致の状態を記憶し、終了番地ま
でアドレス指定を行つた時に前記の記憶状態をチ
ツプ外部に出力すること特徴とする情報処理装
置。1. In an information processing device including a read-only memory on the same chip, an addressing unit that generates addressing information for the read-only memory;
It is equipped with a comparison section that compares the data stored in the read-only memory at the address and the data input from outside the chip, and the address specification section sequentially updates the address and compares it with the input data to determine if they match or do not match. An information processing device characterized by storing a state and outputting the stored state to the outside of a chip when an address is specified up to an end address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58203986A JPS6097449A (en) | 1983-10-31 | 1983-10-31 | Information processor with read-only memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58203986A JPS6097449A (en) | 1983-10-31 | 1983-10-31 | Information processor with read-only memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6097449A JPS6097449A (en) | 1985-05-31 |
| JPH0156480B2 true JPH0156480B2 (en) | 1989-11-30 |
Family
ID=16482890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58203986A Granted JPS6097449A (en) | 1983-10-31 | 1983-10-31 | Information processor with read-only memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6097449A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01118933A (en) * | 1987-10-31 | 1989-05-11 | Nec Corp | Single-chip microcomputer |
| KR0146067B1 (en) * | 1990-03-09 | 1998-09-15 | 문정환 | ROM data protection method and device |
| JP2613674B2 (en) * | 1990-10-31 | 1997-05-28 | シャープ株式会社 | Integrated circuit device |
-
1983
- 1983-10-31 JP JP58203986A patent/JPS6097449A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6097449A (en) | 1985-05-31 |
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