JPH0156571B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a binary counter that is frequently used in digital circuits.

Conventional Structures and Their Problems Conventionally, flip-flop circuits such as those illustrated in FIGS. 1 and 2 have been frequently used as unit stage structures of binary counters using CMOS, for example.

Figure 1 shows a conventional static flip-flop circuit, with a total of 16 elements including P-channel MOS transistors and N-channel MOS transistors, compared to 10 elements in the dynamic flip-flop circuit shown in Figure 2. In comparison, it requires significantly more elements, consumes more power, and has a lower maximum operating frequency.

In addition, the wiring inside the circuit is quite complicated, and two connection lines with the next stage are required (this point can be solved by adding an inverter and creating an 18-element configuration, but the number of elements (increases).

On the other hand, since the circuit shown in FIG. 2 uses gate capacitance to maintain the state of the flip-flop, there is a problem in that it cannot be used at frequencies below 10 KHz from the viewpoint of reliability.

Therefore, in general, a circuit based on the flip-flop circuit shown in Figure 1 is most often used.
When configuring a programmable counter as shown in Fig. 3, each unit stage 10, 20, 30, 40
The internal structure of the device is quite complicated as shown in FIG.

By the way, Figure 3 shows an example of a 4-bit programmable counter (frequency divider).
0, 60, 70, and 80 are program terminals to which the program values of each bit are applied, terminal 90 is a clock signal input terminal, and terminal 100 is a frequency division output terminal.

The unit stages 10, 20, 30, and 40 are connected in cascade to form a down counter. For example, if the program value is a binary number [1000], a down count is performed from this value, and the output of the counter is [1000]. 0000], the detection gate 110 generates an output signal, and the NAND gate 12
RS configured by 0 and NAND gate 130
The flip-flop generates a preset enable signal for each unit stage for a logic 1 period of the clock signal applied to the clock signal input terminal 90, and the counter is again preset to [1000].

Therefore, an output signal having a repetition frequency of one-eighth of the clock signal is obtained from the frequency-divided output terminal 100.

Now, the flip-flop circuit in Figure 4 is
When configured with CMOS, the 2-input NOR gate has 4
A two-input AND gate requires 6 elements when configured individually, resulting in a number of 38 elements per unit stage, which makes it difficult to reduce the chip size when integrating digital circuits using this type of counter. It was a hindrance.

Note that the 2-input AND gate and the 2-input NOR gate have an AND-NOR configuration.
It is possible to reduce the number of elements per unit stage to 30, but in that case, the number of elements connected in series between the feed lines will increase, slowing down the operation speed, and reducing the freedom of wiring. There was a problem that the wiring became complicated as the number of wires decreased.

OBJECTS OF THE INVENTION The present invention realizes a binary counter in which the chip size for constructing a unit stage can be made smaller than before, or in other words, a unit stage can be constructed with a smaller number of wires and elements.

Structure of the Invention The binary counter of the inventive reactor includes a bistable circuit that closes a feedback loop and enters a holding state when the clock signal is logic 0, and a bistable circuit that is supplied with the output of the bistable circuit so that the clock signal becomes logic 0. buffer means for generating an output depending on the output of the bistable circuit when the clock signal is at logic 1; switch means for supplying the output of the buffer means to the bistable circuit when the clock signal is logic 1; a unit stage is constituted by a logic gate supplied with a clock signal and the output of the buffer means;
A plurality of unit stages are connected by supplying the output of the logic gate as a clock signal to the next unit stage,
This reduces the number of elements or wires per unit stage.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 5 shows a circuit connection diagram of a unit stage of a binary counter in an embodiment of the present invention. In the figure, 1 is a negative logic clock signal input terminal.
Gate electrode of transistor, bidirectional switch 14
The output terminal of the inverter 11 is connected to the gate electrode of the P-channel MOS transistor constituting the bidirectional switches 12 and 13.
N channel constituting the bidirectional switch 14
The gate electrode of the MOS transistor and one input terminal of the two-input NAND gate 15 are connected.

Furthermore, the inverter 16, the inverter 17, and the bidirectional switch 13 constitute a bistable circuit 140 in which the feedback loop is closed by the bidirectional switch 13 when the level of the clock signal becomes "H". There is.

The output of the bistable circuit 140 is supplied to the input terminal of the inverter 18 via the bidirectional switch 12, which is closed when the level of the clock signal becomes "H".
The clock signal is supplied to the other input terminal of the NAND gate 15, and the level of the clock signal is "L".
The signal is supplied to the input terminal of the NAND gate 16 via a bidirectional switch 14 that closes when the voltage becomes low.

Further, the output of the NAND gate 15 is supplied to an output terminal 2 for supplying a clock signal to the next unit stage, and the output of the inverter 17 is supplied to a status output terminal 3 of the stage.

Now, FIG. 6 is a time chart for explaining the operation of the circuit of FIG. 5, and the operation of the circuit of FIG. 5 will be explained with reference to FIG.

1a in FIG. 6 is the clock signal waveform supplied to the clock signal input terminal 1, and 12S in FIG.
13S and 14S are bidirectional switches 12,
A time chart showing the open/closed status of 13 and 14.
The solid line portion indicates the closed state, and the broken line portion indicates the open state.

Also, 16a, 17a, 18a, 11 in FIG.
a, 15a are inverters 16, 17, 1, respectively.
8, 11 is the output signal waveform of the NAND gate 15.

In the circuit shown in FIG. 5, the level of the clock signal input terminal is "H" before time _t1 , and the bistable circuit 14
Assuming that the output level of 0 is "L", the bidirectional switches 12 and 13 are in the closed state,
The bidirectional switch 14 is open, the output level of the inverter 18 is "H", and the NAND gate 1
The output level of No. 5 is also "H".

At time _t1 , the clock signal level is “H”
When the switch shifts from 1 to “L”, the bidirectional switch 1
2 and 13 are in the open state, and the bidirectional switch 1
4 is in a closed state, and as a result, the inverter 1
8 is transmitted to the input terminal of the inverter 16, and the output level of the inverter 16 is "L".
Then, the output level of the inverter 17 goes to "H", and the output level of the NAND gate 15 goes to "L".

At time _t2 , the clock signal level is “L”
to "H", the two-way switch 1
2 and 13 are closed, and the bidirectional switch 1
4 becomes open, so that the bistable circuit 1
40 is closed and becomes a holding state, and on the other hand, the output of the bistable circuit 140 is supplied to the input terminal of the inverter 18 via the bidirectional switch 12, so the output level of the inverter 18 is "L". ” and also said NAND
The output level of the gate 15 also shifts to "H" as the output level of the inverter 11 shifts to "L".

At time _t3 , the clock signal level is “H”
When the level changes from t1 to "L", each bidirectional switch, each inverter, and the NAND gate 15 operate in the same manner as at time _t1 , and the same operation is repeated thereafter.

As is clear from comparing the signal waveforms 1a in FIG. 6 and 17a in FIG. 6, it can be seen that the circuit in FIG. 5 also constitutes a general master-slave type flip-flop.

Now, in the circuit of Fig. 5, the bistable circuit 140
has the same configuration as the conventional circuit shown in FIG. The method of keeping the output level of the inverter 17 held by the capacitance of the gate electrode is the same as that of the dynamic counter shown in FIG. 2, and the reliability of its operation is governed by the input clock frequency.

Specifically, the clock signal input terminal 1 in FIG.
The “L” level period of the clock signal supplied to
It is required to be within 50 μsec (if the duty is 50%, it is converted into a frequency of 10 KHz or more).

However, in the flip-flop circuit shown in FIG. 5, only the period during which the clock signal is at the "L" level is regulated, and unlike the conventional dynamic counter, the input frequency itself is not regulated.

That is, as can be seen from FIG. 6, the next unit stage is connected to the NAND gate 15.
A clock signal with the same “L” level period as the input clock signal is generated and sent, so if the frequency of the clock signal applied to the LSB unit stage of the counter is 10KHz or higher, the counter will operate regardless of the number of stages. certainty is guaranteed.

Therefore, unlike conventional dynamic counters, the inversion frequency of the MSB of the counter does not need to be 10KHz or higher, so it cannot be used in most cases except for special systems where the original oscillation frequency of the clock signal is 10KHz or lower. Can be used in any digital system.

Now, when comparing the conventional static type flip-flop circuit shown in FIG. 1 with the flip-flop circuit shown in FIG. 5, there is not much difference in complexity in their basic configurations.

However, when a programmable counter as shown in FIG. 7 is constructed by applying the concept of the flip-flop circuit shown in FIG. 5, the superiority of the present invention over the conventional circuit becomes clear.

Figure 7 shows a 4-bit programmable counter similar to Figure 3, with each unit stage 21
The actual configuration of 0, 220, and 230 is a flip-flop circuit as shown in FIG.

The configuration of the 4th bit (MSB) unit stage is based on the flip-flop circuit shown in Figure 8.
A circuit with the NAND gate 15 removed may also be used,
A much simpler configuration as shown in FIG. 9 is also possible.

Comparing the circuit configuration in Figure 8 with the conventional circuit configuration in Figure 4, it is found that the conventional circuit required 38 elements per unit stage, but the circuit configuration in Figure 8 of the present invention requires 38 elements per unit stage. In a flip-flop circuit, a unit stage can be constructed with 24 elements, and only one clock terminal is required for connection to the previous stage.

In addition, the circuit configuration shown in Figure 9 can be
If used for this purpose, the MSB can be constructed with only 12 elements.

By using such a flip-flop circuit to which the present invention is applied as a unit stage, a programmable counter can be realized with approximately two-thirds the number of elements of a conventional programmable counter. This is because the clock signal is obtained by the NAND gate 15.

This process will be explained using the 4-bit programmable counter shown in FIG. 7 as an example.

Unit stages 210, 220, 230 in FIG.
An outline of the operation will be explained assuming that the flip-flop circuit shown in FIG. 8 is used for the unit stage 240, and the flip-flop circuit shown in FIG. 9 is used for the unit stage 240.
0,240 constitutes a down counter, and when its output reaches [0000], the NAND
The gate 110 generates an output signal, the output level of the NAND gate 120 transitions from "L" to "H", and the output level of the NAND gate 130 goes "H".
to “L”.

The output level of the NAND gate 120 is “H”
When the clock signal is transferred to the unit stage 210 via the NAND gate 150, the clock signal that has been supplied to the unit stage 210 is disabled, and the output level of the NAND gate 150 is fixed at "H".

Therefore, the level of the clock signal input terminal 1 in FIG. 8 is also fixed to "H", and the NAND gate 15
The output level of 0 is also fixed at "L", and the level of the clock signal supplied to the next unit stage also becomes "H".

At this point, bidirectional switches 12 and 13 are closed and bidirectional switch 14 is open.

Also, the output level of each unit stage is “L”
(Here, logic 0 and level "L" correspond.), and the level of program enable terminal 5 is "H".

Therefore, if the level of the data input terminal 6 is "L", the NAND gate 21 for preset
maintains the output level of the NAND gate 21 at "H", and the output level of the NAND gate 19 does not change from "L"; however, when the level of the data input terminal 6 becomes "H", the output level of the NAND gate 21 The level shifts to "L" immediately after the level of the program enable terminal 5 shifts to "H", and as a result, the output level of the NAND gate 19 goes "H".
Then, the output level of the inverter 16 shifts to "L" and the preset is completed.

A similar operation is performed for the circuit of FIG. 9 used for MSB.

That is, immediately before the program enable signal (positive logic) is supplied from the NAND gate 120 in FIG. 7, the output level of the NAND gate 22 is "L" and the output level of the NAND gates 23 and 24 is "H". However, immediately after the program enable signal is supplied, the level of the clock signal input terminal 1 in FIG. 9 shifts to "H".

Therefore, if the level of the data input terminal 6 is "H", the output level of the NAND gate 24 shifts to "H", and the MSB is preset.

In the programmable counter shown in Fig. 7, for example, if [1101] is given as the program data, the output of the counter is [0000].
At the point in time, a program enable signal is supplied to each unit stage, and the output of the counter is preset to [1101].

When the level of the clock signal supplied to the clock signal input terminal 90 shifts to "L", the NAND
The output level of the gate 130 returns to "H", and at that point, the preset operation of each unit stage is completed and the output level of the NAND gate 110 returns to "H", so the output level of the NAND gate 120 becomes "H". Return to L”.

When the level of the clock signal input terminal 90 shifts to "H", the counter restarts down counting from [1101], and eventually the frequency division output terminal 10
From 0, an output signal having a repetition frequency of 1/13 of the input clock frequency is obtained.

In conventional programmable counters of this type,
During programming, it was necessary to supply either a preset signal or a reset signal to all flip-flop circuits constituting each unit stage, but in the programmable counter to which the present invention is applied, the preset signal is supplied only to the unit stage to be preset. The configuration is extremely simple compared to conventional circuits.

Conventionally, when programming a counter, it is necessary to supply a preset signal or a reset signal to all unit stages. The point is that the output signal itself is used.

For example, if the first unit stage 10 in FIG. Since the reset signal is transmitted to the unit stage 20, even if the unit stage 20 is not preset, it is necessary to supply the reset signal at the same timing as the preset timing of the preceding unit stage 10.

However, in the counter shown in FIG. 7, since the status output terminal Q of each unit stage and the output terminal for supplying a clock signal to the next unit stage are operationally separated, the output terminal can be prohibited from shifting to the active level "L".

Specifically, this prohibition is performed by the NAND gate 150, and as is clear from FIG.
When the level of the clock signal input terminal 1 of each unit stage shifts to "H", the level of the output terminal to the next stage is also fixed to "H".

In other words, returning to the basic circuit of the present invention shown in FIG. 5, the NAND gate 15 has one input terminal supplied with the clock signal from the previous stage.
The greatest feature of the present invention is that the output of the counter is used as a clock signal for the next unit stage, and as a result, the configuration of each unit stage constituting the counter can be simplified compared to the conventional one.

By the way, the programmable counter shown in Figure 7 constitutes a down-count type frequency divider, and the output level of all unit stages is "L" immediately before the program enable signal is generated. This is convenient (only the necessary unit stages need be preset), but current flow is rarely used in this way, and preset operations are often required regardless of the counter output. many.

In such a case, as shown in Figure 10,
This problem can be solved by providing a reset signal supply terminal 7 in each unit stage and supplying the reset signal prior to the preset enable signal.

That is, the bistable circuit 140 is configured
The unit stage is reset by applying an "L" level signal to one input terminal of each of the NAND gate 25 and the NAND gate 151 that supplies a clock signal to the next unit stage. The configuration may be such that a preset enable signal is applied.

Note that the reset signal is also supplied to the NAND gate 151, but this can be applied to the first stage clock supply gate 150 (FIG. 7) in the same way as the preset enable signal, and the number of bits of the counter is If it is extremely large, the clock signal transmission element (inverter 11 in Figure 8)
Considering the delay time and reset pulse width of the elements constituting the NAND gate 15, a reset signal is also sent to the NAND gate 15 at each milestone, for example, the 4th bit, the 8th bit, the 12th bit, etc. All you have to do is supply it. (A similar concept can be applied to the preset enable signal.) Now, the flip-flop circuits shown in FIGS. 8 and 10 are both basically expanded versions of the circuit shown in FIG. The flip-flop circuit constituting the unit stage of the binary counter of the present invention is not necessarily limited to the one shown in FIG. 5 or the one based thereon.

For example, when the circuits shown in FIG. 5 are connected in cascade, a negative edge trigger type down counter is constructed, but as shown in FIG. type up counter.

In addition, the circuit of FIG.
3 and 14 are used, but these are immediately replaced by 3.
It can be replaced with a state buffer (3-state inverter).

FIG. 12 shows three three-state inverters 27,
12 shows an example in which a unit stage of the binary counter of the present invention is constructed using 28, 29, two inverters 11, 17, and one NAND gate 15.
7 and 3-state inverter 28 form a bistable circuit 14
It constitutes 0.

A three-state inverter is equivalently an inverter with a switch added to the output side.

In addition, the flip-flop circuit in Fig. 12 is
When expressed as a CMOS circuit connection diagram, it is shown in Figure 13, and the basic number of elements per unit stage is 20.
becomes.

Furthermore, by removing the 3-state inverter 29 from the circuit of FIG. 13 and connecting the bidirectional switch 31 between the output side of the NAND gate 15 and the input side of the inverter 17, the circuit configuration as shown in FIG. becomes even easier.

FIG. 15 is a time chart for explaining the operation of the flip-flop circuit shown in FIG.
a and 15a are inverters 11 and 17, respectively.
NAND gate output signal waveform diagram, 28a, 27
a is a time chart representing the output states of the three-state inverters 28 and 27, respectively, and 31
S is a time chart representing the open/closed state of the bidirectional switch 31.

Before time _t1 , the level of clock signal input terminal 1 is "H" and the output level of inverter 17 is "L".
At that point, the output levels of the three-state inverters 28, 27 and the NAND gate 15 are all "H", and the bidirectional switch 31 is in the open state.

At time _t1 , when the level of the clock signal shifts to "L", the output level of the inverter 11 subsequently shifts to "H", the 3-state inverters 27 and 28 both enter a high impedance state, and the bidirectional switch transitions to the closed state.

One input terminal 15 of the NAND gate 15
The level of x is held at "H" by the three-state inverter 27 until time _t1 ,
Even after the output of the 3-state inverter 27 shifts to the high impedance state, the "H" level is connected due to the accumulated charge, so the output level of the NAND gate 15 shifts to "L", and as a result, the inverter The output level of No. 17 shifts to "H".

At time _t2 , when the level of the clock signal shifts to "H", the inverter 11
At the same time, the output level of the three-state inverters 27 and 28 shifts to "L", and the bidirectional switch 31 shifts to the open state.

Further, as the output level of the inverter 11 shifts to "L", the output level of the NAND gate 15 returns to "H".

At time _t3 , the level of the clock signal is
When it shifts to "L", the inverter 11
The output level of the three-state inverters 27 and 28 shifts to a high impedance state, and the bidirectional switch 31 shifts to a closed state.

At this time, the level of one input terminal 15x of the NAND gate 15 remains at the previous "L" level, so the output level of the NAND gate 15 does not change from "H"; Since the signal is transmitted to the input terminal of the inverter 17 via the bidirectional switch 31, the output level of the inverter 17 shifts to "L".

At time _t4 , when the level of the clock signal shifts to "H", the inverter 11
The output level of the three-state inverters 27 and 28 shifts to "L", and the output level of the three-state inverters 27 and 28 shifts to "H".
At the same time, the bidirectional switch 31 shifts to the open state.

Thereafter, similarly, the output level of the inverter 17 changes when the level of the clock signal changes from "H" to "L".

Now, when an external set terminal is provided in the flip-flop circuit shown in FIG. 14, the circuit configuration becomes as shown in FIG. 16.

In FIG. 16, the three-state inverter 28
Instead, a three-state NOR 32 is used, one input terminal of which is connected to the output terminal of the inverter 17, and the other input terminal connected to the external set terminal 101.
It is connected to the.

If a 4-bit programmable counter similar to that shown in FIG. 3 is configured using the flip-flop circuit shown in FIG. 16 as a unit stage, it will be as shown in FIG. 17.

In FIG. 17, unit stages 250, 26
0 and 270 are both flip-flop circuits shown in FIG. 16, and a simple flip-flop circuit as shown in FIG. 18 can be used for the unit stage 280.

In FIG. 17, P-channel MOS transistors 51, 61, 71, 81 and N-channel MOS
The transistors 52, 62, 72, and 82 each constitute a toggle switch, and while the counter is counting, the output level of the NAND gate 130 is "H", so the N-channel MOS transistor is turned on. state, 16th
The 3-state NOR 32 in the figure works as a 3-state inverter, and the NAND gate 22 in FIG.
works just as an inverter, but the NAND
When the output level of the gate 130 becomes “L”, N
All channel MOS transistors 52-82 are turned off, and instead, P-channel MOS transistors 51-91 are turned on to perform a preset operation.

The programmable counters shown in FIGS. 16 and 17 can be configured with only 22 elements per unit stage, including toggle switches, and the number of elements is significantly reduced compared to the conventional one.

By the way, in the above explanation, CMOS circuits were used as examples for both the conventional example and the embodiment of the present invention, but the binary counter of the present invention is not limited to CMOS circuits, and although there are differences in the degree of implementation effect, It can be applied to NMOS, PMOS, and even bipolar circuits.

Effects of the Invention As described above, in the present invention, the clock signal is set to logic 0.
(In the explanation of the embodiment, the expressions "L" level and "H" level are used, but when "H" level corresponds to logic 0, "L" level corresponds to logic 1, and conversely, "L" level corresponds to logic 1. ``When the level corresponds to logic 0, the ``H'' level corresponds to logic 1. Buffer means (fifth
In the embodiments shown in FIGS. 8, 10, and 11, the bidirectional switch 12 and the inverter 18 constitute the buffer means, and in the embodiments shown in FIGS. 12, 13, 14, and 16, the State inverter 27 constitutes buffer means. ), a switch means (corresponding to the bidirectional switch 14 or 31, or the three-state inverter 29) for supplying the output of the buffer means to the bistable circuit when the clock signal is logic 1; A unit stage is constituted by a logic gate (corresponding to the NAND gate 15 or NOR gate 26) to which a clock signal and the output of the buffer means are supplied, and the output of the logic gate is used as a clock signal for the next unit stage. It is characterized by a plurality of unit stages connected together depending on the logic gate supplied, and has a reset and set function by using a novel configuration in which the output of the logic gate is used as a clock signal for the next unit stage. Even basic circuits that do not have a conventional circuit have simpler configurations than before, and as the functions of unit stages become more complex, such as reset functions, set functions, and even programmable functions, the number of elements or wires is reduced compared to conventional circuits. As a result, the scale of a system incorporating this type of counter has been reduced, which not only reduces the chip size when converting the system to an IC, but also reduces power consumption, improves reliability, and improves production yield. The effects of the present invention, such as connection, are significant.

Further, the embodiment shown in FIG. 5 and the embodiment shown in FIG. 14 most effectively achieve the object of the present invention, and in both cases, a unit stage is constructed with the minimum necessary number of elements and wiring.

[Brief explanation of drawings]

1 and 2 are circuit wiring diagrams showing unit stages of a conventional binary counter, and FIG. 3 is a circuit wiring diagram showing a conventional programmable counter.
4 is a circuit connection diagram showing the configuration of the unit stage of the counter in FIG. 3, FIG. 5 is a circuit connection diagram showing an embodiment of the present invention, and FIG. 6 is for explaining the circuit operation of FIG. 5. 7 is a circuit wiring diagram of a programmable counter to which the present invention is applied,
Fig. 8 is a circuit wiring diagram of the unit stage, Fig. 9 is a circuit wiring diagram showing an example of the configuration of the MSB of the counter,
Figure 10, Figure 11, Figure 12, Figure 13, Figure 1
4 is a circuit connection diagram showing another embodiment of the present invention, FIG. 15 is a time chart for explaining the circuit operation of FIG. 14, and FIG. 16 is a circuit showing another embodiment of the present invention. Connection diagram, FIG. 17 is a circuit connection diagram showing another configuration example of a programmable counter to which the present invention is applied, and FIG. 18 is a circuit connection diagram of the counter in FIG. 17.
FIG. 2 is a circuit wiring diagram showing a configuration example of a unit stage that can be used for MSB. 14... Bidirectional switch, 140... Bistable circuit, 15... NAND gate, 26... NOR gate, 31... Bidirectional switch, 27... 3-state inverter, 29... 3-state inverter,
18...Inverter, 12...Bidirectional switch.

Claims (1)

[Scope of Claims] 1. A bistable circuit whose feedback loop closes and enters a holding state when the clock signal is logic 0; buffer means for generating an output dependent on the output of the ballast circuit; switch means for supplying the output of the buffer means to the bistable circuit when the clock signal is logic 1; A unit stage is configured by a logic gate to which the output of the buffer means is supplied, and a plurality of unit stages are connected by supplying the output of the logic gate as a clock signal to the next unit stage. A binary counter with . 2 Connect the input terminal of the inverter to the output side of the bistable circuit via a second switch means, and
2. The binary counter according to claim 1, wherein the switch means and the inverter constitute buffer means. 3. The inverter and the first 3-state inverter constitute a bistable circuit, the second 3-state inverter constitutes a buffer means, a clock signal is supplied to one input terminal, and a bistable circuit is supplied to the other input terminal. A patent characterized in that a switch means which is opened and closed according to the logic level of the clock signal is connected between the output terminal of the logic gate to which the output of the second three-state inverter is supplied and the input terminal of the inverter. A binary counter according to claim 1.