JPH0157422B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for processing PCM (Pulse Code Modulation) signals, and more specifically, the present invention relates to a method for processing PCM (Pulse Code Modulation) signals, and more specifically, the present invention relates to a method for processing PCM (Pulse Code Modulation) signals, and more specifically, It is possible to read PCM signals without being affected by changes in the ratio (D/S ratio) of PCM signals and synchronization signals.
Related to PCM signal processing method.

A method of converting an analog signal such as an audio signal into a PCM signal and recording and reproducing it using a VTR is already well known. By the way, when a composite PCM signal is transmitted, the synchronization signal component is distorted due to a drop between the base and emitter of a transistor in the transmission circuit, and the ratio between the amplitude of the PCM signal and the amplitude of the synchronization signal changes. The slice level for reading the PCM signal is determined based on the synchronization signal or the peak-to-peak level of the composite PCM signal.
Since it is determined based on the peak, as mentioned above,
When the ratio of PCM signal (data) and synchronization signal changes, the slice level also changes, making it impossible to obtain the optimal slice level. The fact that the optimum slice level cannot be obtained means that it is not possible to obtain a slice output waveform with a duty ratio of 50% when a signal repeats logic "1" and "0". If the slice level changes significantly and the duty ratio also changes significantly, it becomes impossible to accurately read data using a clock signal (timing pulse).

Therefore, the purpose of the present invention is to
is not affected by changes in the ratio between
An object of the present invention is to provide a PCM signal processing method that can read PCM signals.

To achieve the above object, the present invention transmits a composite PCM signal in a television signal format including a PCM signal, a synchronization signal, and a slice level signal having an amplitude approximately half of the amplitude of the PCM signal. The present invention relates to a PCM signal processing method characterized by extracting and holding the slice level signal from the composite PCM signal, and slicing the PCM signal using the held slice level.

According to the above invention, slice processing that is not easily influenced by the nonlinear characteristics of the transmission system becomes possible. That is, television signal format signals are easily affected by the nonlinear characteristics of the transmission system. Therefore, it is important to make the slice level signal less susceptible to the nonlinear characteristics of the transmission system. In the present invention, we focused on the fact that the amplitude of about half of the amplitude of the PCM signal is least affected by nonlinear characteristics, and set the level of the slice level signal to have about half of this amplitude, so that the nonlinear characteristics of the transmission system This enables slicing with less influence of characteristics, making it possible to read data accurately.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a PCM recording method using a VTR according to an embodiment of the present invention. This first
In the figure, 1, 2, 3, and 4 are input terminals for inputting four channels of audio signals. Four sample and hold circuits 5, 6, 7, 8 coupled to four input terminals 1, 2, 3, 4, respectively
is a circuit that is controlled by the output pulses of a timing pulse generator 10 that generates various timing pulses based on a reference oscillator 9, and samples and holds an analog signal at a predetermined sampling period. four analog-to-digital converters 11 coupled to the outputs of the sample and hold circuits 5, 6, 7, 8 and coupled to a timing pulse generator 10;
12, 13, and 14 convert sampled analog signals into digital signals, that is, PCM signals. In this example, 12 bits equals 1 word.
The PCM signal is output in the form of a parallel signal, and each analog-to-digital converter 11 to 14 is provided with 12 output lines, and 4 channel signals are sampled at the same time, so one sample ultimately yields a 48-bit output. It will be done. 15 is a parallel-to-serial converter, which includes four analog-to-digital converters 11 to 14;
The parallel format PCM signal obtained from the PCM signal is converted into a serial format based on the control of timing pulses.
It converts it into a PCM signal.

The vertical parity memory 16 coupled to the parallel-to-serial converter 15 has five rows of memory A, B, C, D, and E, and is controlled by a write clock provided by the timing pulse generator 10. Data is stored in the form of five lines. In this embodiment, 48 bits of 4 channels obtained from the first sample are stored in the A memory, 48 bits obtained from the second sample are stored in the B memory, and similarly, 48 bits of the third sample are stored in the B memory. The bits are stored in C memory, the 48 bits of the fourth sample are stored in D memory, and the 48 bits of the fifth sample are stored in E memory. That is, this memory 16 has 240 bits 20
Words are stored as one block and in the form of five lines.

A vertical parity bit adding circuit 17 to which the five output lines of the memory 16 are coupled forms a vertical parity bit of a data block consisting of five rows and adds it to the output of the data block. Note that 48 vertical parity bits are obtained corresponding to the 48 bits of each row, and under the control of the timing pulse generator 10, six vertical bits including the vertical parity bit are simultaneously output from six output lines.

CRC memory 18 coupled to the six output lines of the vertical parity bit addition circuit 17 and coupled to the timing pulse generator 10;
is a cyclic code, or CRC code (Cyclic
A data block of five rows and a vertical parity bit are stored in order to generate and append a redundancy check code. Note that the input to the memory 18 is given 6 bits simultaneously by 6 output lines, but the output is converted to a serial PCM signal and is applied to the first and second rows of the data block.
Rows..., row 5, vertical parity bits are transmitted in this order. The CRC code adding circuit 19 forms a CRC code for each row of 48 bits, adds a CRC code of 12 bits after each row, and adds a CRC code of 60 bits to the end of each row.
It is sent as a line. The CRC code and its formation method are described, for example, in the publication "Basic Knowledge of Data Transmission" published by the Telecommunications Association, from page 154 onwards.
Since it is publicly known, such as on page 158, detailed explanation will be omitted. An interleaving memory 20 to which the output line of the CRC code addition circuit 19 is coupled and the timing pulse generator 10 is coupled includes a vertical parity bit and a CRC code (CRC bit).
A memory for interleaving, that is, dispersing, the data in a PCM signal string, in which the data read address circuit does not read data in sample order, but reads data in skips, thereby distributing the data in the PCM signal string. It forms the

A time compression memory 21 coupled to the output line of the interleaving memory 20 and coupled to the timing pulse generator 10 is used to provide periods corresponding to the vertical and horizontal blanking periods in the television signal. This is a memory that compresses the PCM signal sequence by a period of time.

Reference numeral 22 denotes a synchronization signal generation circuit which is controlled by the output of the timing pulse generator 10 and generates synchronization signals corresponding to the vertical synchronization pulse, equivalent pulse, and horizontal synchronization pulse of the television signal. This embodiment does not process video signals, but audio signals.
For convenience of explanation, the various synchronization pulses will be referred to as vertical synchronization pulses, equivalent pulses, and horizontal synchronization pulses, as in the case of television signals.

A resynchronization signal generation circuit 23 coupled to the synchronization signal generation circuit 22 generates a resynchronization horizontal address signal corresponding to each horizontal scanning period in order to obtain resynchronization. In this embodiment, a 4-bit address signal is written based on the first horizontal scanning period in which data is first placed in the vertical scanning period, and when it becomes [1111] in the 16th horizontal scanning period, From the 17th horizontal scanning period, the address returns to [0000] and is written again.
Of course, the number of bits may be increased and different address signals may be written in each horizontal scanning period. Multiplexer 24 outputs from time compression memory 21
By selectively passing the PCM signal train and the 4-bit resynchronization horizontal address signal generated from the resynchronization signal generation circuit 23, a PCM signal train including the resynchronization horizontal address signal is sent out. be. The resynchronization horizontal address signal described above is output when a horizontal synchronization pulse is lost due to editing or dropout of a recording signal, and is used to perform synchronization following this signal.

A white level signal generating circuit 25 coupled to the synchronizing signal generating circuit 22 is a circuit for inserting an auxiliary signal corresponding to the white level of the television signal into a portion other than the data portion of the PCM signal string. In this embodiment, this white level signal generation circuit 2
5, 3H in even field (however H
is one horizontal scanning period) after the vertical sync pulse interval
A white level signal is sent in the 3H to 5H period, and a white level signal is sent in a 9.5H period after the 245H data period after the 3H white level period.
In addition, a white level signal is sent in the 3H to 4.5H period after the 3H vertical synchronization pulse period of the odd field, and then 245H after this 2.5H white level period.
A white level signal is sent in the 10H period after the data period. The white level signal is included in a predetermined portion of the PCM signal train together with a synchronization signal and the like in the mixer 26.
If you include the white level signal in advance like this,
The VTR's AGC circuit operates based on this white level and is set to a level lower than the white level.
The amplitude of the PCM signal is prevented from increasing above the white level.

A data slice level generation circuit 27 coupled to the timing pulse generator 10 and the synchronization signal generation circuit 22 generates a signal immediately after the 3H vertical synchronization pulse section.
It uses a 2H equivalent pulse interval to generate a signal with an amplitude corresponding to the data slice level. This data slice level signal is sent to the mixer 26
where it is included in a predetermined part of the PCM signal train. If the data slice level is included in the PCM signal train in advance in this way, even if the ratio between the data amplitude and the synchronization signal amplitude fluctuates, the data slice level will be determined without being affected by this. It becomes possible to read accurately.

The VTR 28 schematically shown surrounded by a dotted line is U-
A household VTR such as MATIC or BETAMAX, which has a known AGC circuit 29, a pre-emphasis circuit 30, and a clamp/white clip circuit 3.
1. Includes FM modulation circuit 32, recording amplifier circuit 33, magnetic head 34, etc., and is transmitted by wire or wirelessly.
FM recording is performed on a magnetic tape 35 running a PCM signal train. Although not shown, the VTR 28 has a low-pass filter for removing noise in its input circuit, and further includes a tape running system, a magnetic head rotation mechanism, and the like.

The PCM signal recording method using the PCM signal recording apparatus shown in FIG. 1 will be described in more detail with reference to waveform diagrams, time charts, etc.

For example, when an audio analog signal as shown in FIG. 2 is input from the input terminal 1 of the first channel, the analog signal is sequentially sampled at a predetermined sampling period in the sample-hold circuit 5, and the analog signal shown in _FIG . Sampling signals shown as 1b ₁ , 1c ₁ , 1d ₁ , 2a ₁ . . . are obtained. The sampling signals in FIG. 3 are sequentially processed by the A-D converter 11.
Converted to PCM signal, sampling signal 1a ₁ ,
1b ₁ , 1c ₁ , 1d ₁ , 1e ₁ , 2a ₁ . . . corresponding to the data shown in FIG. 4A, that is, the PCM signals 1A ₁ , 1B ₁ ,
The PCM signal sequence includes 1C ₁ , 1D ₁ , 1E ₁ , 2A ₁ . . . These data are sent out in parallel from the analog-to-digital converter 11 in the form of 12 bits per word and input to the parallel-to-serial converter 15.
I have just mentioned the first channel, but the second to fourth channels
Similar signal processing is performed on the second channel in synchronization with the first channel, and the second channel's analog
The digital converter 12 outputs data in the order of 1A ₂ , 1B ₂ , 1C ₂ , 1D ₂ , 1E ₂ , 2A _{2 .} . . as shown in FIG. From the converter 13, as shown in FIG. 4C, 1A ₃ , 1B ₃ , 1C ₃ , 1D ₃ , 1E ₃ , 2
Data _is output in the order of _{A 3 .}
Data is output in the order of D ₄ , 1E ₄ , 2A ₄ . . .
Since each data of each channel is one word of 12 bits, one sample of 48 bits of signal is input to the parallel-to-serial converter 15 at the same time. That is, in FIG. 4, four pieces of data arranged vertically are sent out simultaneously.

The four-channel data input in parallel form is converted into a serial form PCM signal as shown in FIG. 5 by a parallel-to-serial converter 15. That is, 1A ₁ , 1A ₂ , 1
As shown by A ₃ , 1A ₄ , 1B ₁ , 1B ₂ , 1B ₃ , 1B ₄ , . . . , the PCM signal strings are arranged in channel order and sample order.

Such a PCM signal train is transmitted to the next stage of memories A, B,
Data 1A ₁ , 1A ₂ , 1A ₃ , 1A ₄ shown in row A of FIG. Data 1B ₁ , 1 shown in line B of Figure 6
B ₂ , 1B ₃ , 1B ₄ are written sequentially, and the memory C
The data 1C ₁ , 1C ₂ , 1 shown in the C line of FIG.
C ₃ , 1C ₄ are written in sequence, and data 1D ₁ , 1D ₂ , 1D ₃ , 1 shown in row D of FIG.
D ₄ is sequentially written, and data 1E ₁ , 1E ₂ , 1E ₃ , and 1E ₄ shown in row E of FIG. 6 are sequentially written into the memory E. Since memories A, B, C, D, and E are arranged in parallel, the data arrangement in memory 16 substantially matches the arrangement shown in FIG.

In FIG. 6 and subsequent drawings, the 20 data 1A ₁ to 1E ₄ shown at time t _{1 to t 5 in} FIG. Similarly, 20 pieces of data are sequentially processed as a unit block.

The vertical parity bit addition circuit 17 forms 5-bit parity bits arranged vertically in the data block of 5 rows and 4 columns shown in FIG. 6, and adds them to the end of each column. For example, 12 bit data 1A ₁ ,
Find the parity bit for the first bit of 1B ₁ , 1C ₁ , 1D ₁ , 1E ₁ , the parity bit for the second bit, and the parity bit for the 12th bit in the same manner, and calculate the parity bit for the 12th bit.
As shown in the figure, for convenience, the vertical parity data in the first column is assumed to be 1F ₁ . Similarly, the vertical parity bits are calculated for the second to fourth columns, and the vertical parity data 1F ₂ ,
Let them be 1F ₃ and 1F ₄ . In Figure 7, rows A to E are
Since it has a 48-bit configuration, the number of vertical parity bits in row F is 48. Note that the vertical parity bit adding circuit 17 outputs 6 bits each in matrix and bit units.

In the CRC code addition circuit 19, CRC codes for rows A to F shown in FIG. 7 are formed row by row.
For example, the four data in row A are 1A ₁ , 1A ₂ , 1A ₃ ,
A 12-bit CRC code is added to _1A4 .
1A ₅ , 1B ₅ , 1C ₅ , 1D ₅ , 1E ₅ , shown in FIG.
_1F5 is CRC data of rows A to F, each consisting of 12 bits. CRC code addition circuit 19
Although the data is not output in the matrix form shown in FIG. 8, the data is shown in the matrix form similar to that in FIG. 7 to facilitate understanding of the CRC code. Actually, CRC code addition circuit 1
9, 1A ₁ , 1A ₂ , 1 as shown in FIG.
A ₃ , 1A ₄ , 1A ₅ , 1B ₁ , 1B ₂ , 1B ₃ , 1B ₄ ,
Data is output in the order of 1B ₅ , 1C ₁ , 1C ₂ , . . . , 1F ₅ . Further, since the continuously sent data is processed with 20 data as a unit data block, the data block arrangement shown in FIG. 9 is generated. Therefore, when all the data of the first data block shown in FIG.
A ₁ , 2A ₂ , 2A ₃ , 2A ₄ , 2A ₅ , 2B ₁ ,...2F ₅
The data of the 49th data block is also sent out in this order.

FIG. 10 shows the order of data written from the CRC code addition circuit 19 to the interleaving memory 20. The interleaving memory 20 has a capacity to store at least all the data of the first to forty-ninth data blocks, and for convenience, the interleaving memory 20 has a capacity to store all data of the first to forty-ninth data blocks.
The data up to the data block is defined as a large data block, and data is distributed within this large data block. The data is distributed in the arrangement shown in FIG. 11 based on the read address designation of the interleaving memory 20. That is, after sequentially reading out the data in the first row and first column of the 49 data blocks illustrated in FIG. 9 to form _a data array of 1A ₁ , 2A ₁ , 3A ₁ , . Read the data in the 1st row and 2nd column sequentially and read 1A ₂ , 2A ₂ , 3A ₂ , ...49
Form a data array of A ₂ , and similarly the 1st row, 3rd column,
After reading the data in the 1st row, 4th column, and 1st row, 5th column, the data in the 2nd row, 1st column is sequentially read out, resulting in a data array of 1B ₁ , 2B ₁ , 3B ₁ , ...49B ₁ 1F ₅ , 2F ₅ , 3F ₅ , by sequentially reading out the data in the 6th row and 5th column.
... _49F5 data array is formed, data distribution within the large data block is completed, and data distribution processing of the next large data block is started. By distributing data in this way, even if a data error occurs due to dropout, the probability that data errors will occur consecutively in the normal data array is reduced, making it possible to perform good recording and playback. .

The PCM signal train in which data is arranged in a distributed manner is time-compressed to the extent that vertical blanking and horizontal blanking can be provided in the time compression memory 21. Equivalent pulse, white level signal,
After data slice level signal is added
It is sent to the VTR 28 by wire or wirelessly. VTR28
The signal sent to
It is a PCM signal. To explain this composite PCM signal in detail, it is a signal in which even fields and odd fields are arranged alternately like a television signal, and in the even field shown in FIG. A vertical synchronization pulse interval T ₁ is provided, followed by a 2H data slice level signal interval T ₂ containing an equivalent pulse 37, in which a V ₂ volt slice level signal 38 is provided. In this embodiment, when V ₀ is 0 volts, the voltage V ₁ which is the amplitude of the synchronization signal is 0.3 volts, and the slice level signal 38
The maximum voltage V ₂ of the data signal 39 is set to 0.45 volts, the maximum voltage V ₃ of the data signal 39 is set to 0.6 volts, and the maximum voltage V ₄ of the white level signal 40 is set to 1 volt.

The slice level signal 38 is used when slicing the data signal 39 during playback.
Since the amplitude of the slice level signal 38 with respect to V ₁ is 0.15 volts while the amplitude of the data signal 39 with respect to V ₁ is 0.3 volts, the slice level voltage V ₂ is at the center of the amplitude of the data signal 39. positioned. This slice level signal 38 is extracted by a sample and hold circuit during playback, and is used to determine the slice level of the data signal, as will become clear from the description below.

A white level signal 40 is arranged as an auxiliary signal in a 3H white level signal section _T3 including an equivalent pulse 37 and a horizontal synchronizing pulse 41 after the slice level signal section _T2 . This white level signal 40 is
It serves as a reference for the AGC circuit 29 of the VTR 28, and is used for data signals 39 and slice level signals 38.
It has a function of preventing the amplitudes of these signals from increasing even if they pass through the AGC circuit 29.

In the data signal section _T4 of 245H after the white level signal section _T3 , data is sequentially arranged as shown in FIG. (not shown in the figure). In this example,
As shown in Figure 13, 1H corresponds to 260 clocks (however, the clock frequency is 4.095MHz), the horizontal synchronizing pulse 41 has a time width corresponding to 20 clocks, the back porch corresponds to 14 clocks, and the data signal 39 The section corresponds to 220 clocks (bits), and the front porch corresponds to 6 clocks. Then, as shown in FIG. 14, the first four bits of the 220 bits are used to generate the resynchronization horizontal address signal 42, for example, [0000], [0001], [0010], [0011].
It is included in each horizontal scanning period in the form of . That is,
The first data signal D ₁ is attached with an address signal of [0000], the second data signal D ₂ is attached with an address signal of [0001], and the third data signal D ₃ is attached with an address signal of [0000]. [0010] address signal is attached, and the fourth data signal _D4 is [0011].
An address signal is attached thereto, and address signals are similarly attached up to the 245th data D ₂₄₅ . However, in this embodiment, since the address signal is formed by 4 bits, when it reaches [1111], an address signal of [0000] is added again. Therefore, resynchronization is actually possible only when a dropout occurs in the horizontal synchronization pulse 41 up to the 16th data _D16 . However, in this device, the editing point is set between the 9th data D ₉ and the 15th data D ₁₅ , so the jump in the time axis occurs almost everywhere, and almost no jump occurs in other parts. This does not occur at all, so there is virtually no problem. If it is desired to perform a resynchronization operation even when a jump in the time axis occurs due to a dropout, a different address signal is added to all 245H using, for example, an 8-bit horizontal address signal.

Returning to FIG. 12A, a 9.5H white level signal section _T5 is provided again after the 245H data section _T4 ,
A white level signal 43 is added here. After this white level signal 43, a vertical synchronizing pulse section _T6 of an odd field of the next frame is provided. In the odd field shown in FIG. 12B, after the 3H vertical synchronization pulse section T ₆ , the 2H slice level signal section T ₇ , the white level signal section T ₈ ,
245H data interval T ₉ , 10H white level signal interval
T ₁₀ are provided in sequence. and data interval
A horizontal address signal is added to each horizontal scanning period of _T9 as in the even field. In this embodiment, in order to distinguish between even and odd fields, the width of the white level signal section is changed between even and odd fields.

The waveforms A and B in FIG. 12 are input to the VTR 28 in FIG. However, although the data signal 39 is shown for explanatory purposes in FIGS. 12A and 12B, it is in the output state of voltage V ₃ in response to logic "1" as shown in FIG. This is a binary waveform signal that becomes the output state of V ₁ in response to “0” of .
When a composite PCM signal such as that illustrated in _FIG . level)
It will never be lifted up. Therefore, the data signal 39 and the slice level signal 38 pass through the AGC circuit with almost no influence from the AGC.

When the composite PCM signal shown in FIG. 15A passes through the pre-emphasis circuit 30, the data signal 39 is a high frequency signal compared to a synchronization signal, etc., so the amplitude is approximately equal to the white level voltage V ₄ as shown in FIG. 15B.
increased to. A clamp/white clip circuit 31 is provided at the output stage of the pre-emphasis circuit 30, and a white level voltage _V4 or above is cut off, but in the case of this embodiment, the data signal 39 is only raised to the white level. because there is,
Virtually unaffected by white clip, the first
The waveform shown in FIG. 5B is sent to the FM modulation circuit 32. In the conventional method that does not add a white level signal, the data signal is at the maximum level, so the data signal
The data signal is raised to a white level by the AGC circuit 29, and when it passes through the pre-emphasis circuit 30, only the data signal belonging to a higher frequency is raised to a white level voltage _V4 or higher as shown by the dotted line in FIG. 15C.
When passing through the clamp/white clip circuit 31 in the next stage, the beginning of the data signal 39 is cut off at the white level, resulting in a distorted waveform.If the slice level is set at the center of the data signal 39, "1" and "0" Even if the signal is repetitive, the duty ratio is
It is not 50%, and the state is Ta>Tb. and,
If Ta and Tb differ significantly, the clock pulse will
Ta and Tb will no longer be entered regularly, making it impossible to read the data accurately. On the other hand, in the case of this embodiment, no waveform distortion occurs, so
It becomes possible to read data accurately.

The waveform shown in FIG. 15B is generated by the FM modulation circuit 32.
converted to FM waves. That is, the white level logic "1" is converted to 5.4 MHz, the logic "0" is converted to 4.6 MHz, and the _V0 level synchronization signal is converted to an FM wave of 3.8 MHz, which is recorded on the magnetic tape 35.

Next, a reproduction apparatus and method will be explained.

In FIG. 16 showing the PCM playback device, 44
is the same as or different from the recording VTR, and includes a preamplifier 45 and a limiter 4 in addition to the magnetic head 34.
6, FM demodulator 47, de-emphasis circuit 4
8 and amplifiers 49 in sequence. VTR44
signal/synchronization signal separation circuit 50 coupled to the output of
1 separates a composite PCM signal into a synchronization signal and a PCM signal, and this embodiment is constructed as shown in FIG. 17.

The time axis expansion memory 51 connected to the output of the separation circuit 50 restores the time axis compressed by the recording system, and at the same time absorbs jitter etc. to obtain a data array with equal intervals without time axis fluctuation. be. Note that write address control of this memory 51 is performed by a write address circuit 52 having a resynchronization function, and read control is performed by the output of a timing pulse generator 53. The write address circuit 52 generates a write address signal based on the synchronization signal and address signal applied from the separation circuit 50 and the clock signal applied from the reference oscillator 9, and is specifically configured as shown in FIG. has been done.

A deinterleaving memory 54 connected to the output of the time axis expansion memory 51 is the 11th memory in the recording system.
This is for reading out the interleaved data as shown in the figure and restoring it to the data array shown in FIG. 10 based on address control.

A CRC check circuit 55 connected to the output of the deinterleaving memory 54 is an error detection circuit that divides the transmitted signal by a generating polynomial, and if it is evenly divisible, there is no error, and if it is not, there is an error. It is. Therefore, a CRC check is performed for each row of each data block shown in FIG. The result of the CRC check is then sent to an error correction circuit 58 and a correction circuit 60.

Data is sequentially sent to the vertical parity check memory 56 connected to the output of the CRC check circuit 55, regardless of the result of the CRC check, and is distributed to memories A, B, C, D, E, and F. is written. In other words, memory A has A in FIG.
Memory B has row B in Figure 7, Memory C has row C in Figure 7, Memory D has row D in Figure 7, Memory E has row E in Figure 7, and memory F has row C in Figure 7. The data in row F in FIG. 7 is sequentially written. Of course, other data blocks are also written in the same way.

A vertical parity check circuit 57 coupled to the output of the memory 56 checks the parity bits based on the bits read from the memories A, B, C, D, E and the parity bits previously generated in the recording system read from the memory F. This circuit compares the vertical parity bit with the vertical parity bit and determines whether there is a vertical parity error. To describe the vertical parity check in more detail with reference to FIG. 7, for example, the first column of data 1A ₁ , 1B ₁ ,
It is determined whether the parity bits of each bit of 1C ₁ , 1D ₁ , 1E ₁ match the parity bit of vertical parity data 1F ₁ determined at the time of recording, and if they do not match, it is determined as a vertical parity error, and if they match, it is determined that there is no error. . The vertical parity check result is
The signal is sent to the error correction circuit 58.

The error correction circuit 58 coupled to the output of the vertical parity check circuit 57 receives the PCM data in memories A to E regardless of the result of the parity check.
Feed in on the book's output line. Error correction circuit 5
The data arrangement in 8 is as shown in FIG. 6, and in terms of data it is a data block of 5 rows and 4 columns, and in terms of bits it is a 5 x 48 bit bit block. This error correction circuit 58
The error is corrected only when it is notified from the check circuit 55 that only one row in the same data block is erroneous. If there is an error in two or more lines, it cannot be corrected. To describe the error correction operation in more detail, the vertical parity check circuit 57 sequentially performs a vertical parity check of the data block shown in FIG. 6 48 times from left to right. When a parity error is detected by performing the vertical parity check in this way, the CRC check circuit 55 inverts the bits in the row determined to be a CRC error to make them correct bits. For example, if it is detected that row B of the data block in FIG. It turns out that the first bit of the intersection data 1B ₁ in the first column is incorrect, so if it is "0" it is inverted to "1", and if it is "1" it is inverted to "0". , set the correct bit. This error correction circuit 5
8 is 100% correctable if the CRC error is in one line and the parity error is 12 bits or less, and 99.95% if the parity error is 13 bits.
It is correctable, and if the parity error is 14 bits or more, it is 99.975% correctable.

A serial-to-parallel converter 59 coupled to the five output lines of the error correction circuit 58 converts the data array of FIG. 6 into the data array of FIG. 5, and outputs each data in a 12-bit parallel format. It is something.
Therefore, this converter 59 is provided with 12 output lines, and data is output in units of 12 bits per word, and is input to the correction circuit 60 at the next stage. Correction circuit 6
0 works when the correction command circuit 66 detects a CRC error in two or more lines. The correction command circuit 66
It is connected to the CRC check circuit 55, detects by the CRC check that a CRC error has occurred in two or more lines, and operates the correction circuit 60. In the correction circuit 60, all data in the rows determined to be erroneous in the CRC check are corrected. At that time, correction processing was performed on four channels by division. Further, if errors do not occur continuously in each channel, correction is performed by average value interpolation, and if errors occur continuously, correction is performed by holding the previous value. Average value interpolation is performed using the known method of calculating the average value using data before the error data and data after the error data, and using this as the error data part.Previous value hold is performed using the data immediately before the error data. This is done using any known method of preserving data. However, in this embodiment, since the data is interleaved, the probability of successive errors in the data is extremely low, and most corrections can be made by interpolation.

The corrected PCM signal train is sent to four digital-to-analog converters 61, where it is converted into analog signals for each channel. That is, it is restored to an analog signal as shown in Fig. 2, and the first, second,
It is output from the third and fourth output terminals 62, 63, 64, and 65. Note that various timing pulses are generated from the timing pulse generator 53, and the time axis expansion memory 51 and the deinterleaving memory 5
4, applied to a CRC check circuit 55, a memory 56, a parity check circuit 57, an error correction circuit 58, a serial-parallel converter 59, a correction circuit 60, and a digital-to-analog converter 61.

Next, the separation circuit 50 shown in FIG. 16 will be explained in more detail with reference to FIG. 17. Composite obtained from VTR44
When the PCM signal is input to the input terminal 67, the clamp circuit 68 connected thereto outputs the synchronizing signal.
Clamped based on V ₀ level. First, second, and third comparators 69, 70, and 71 are connected to the output line of the clamp circuit 68, and a sample and hold circuit 72 is further connected.

The sample and hold circuit 72 is a circuit that samples and holds the slice level signal during the τ period determined by the output pulse of the monostable multivibrator 73. The reference slice level sampled and held in the previous cycle is attenuated to 1/3 by the 1/3 attenuator 74, and this becomes the reference level of the second comparator 70. The sample held level is
If L ₂ =0.45 volts, then L ₁ =0.15 volts is the reference level for comparator 70. On the other hand, the clamp circuit 68 outputs a waveform as shown in FIG. 18A and serves as one input of the second comparator 70, so the comparison reference level _L1 is set at the position shown in FIG. 18A. state, and the second comparator 7
A synchronizing signal is obtained on the 0 output line as shown in FIG. 18B. Since the low pass filter 75 is also connected to the output line of the second comparator 70,
The vertical synchronization signal is separated as shown in FIG. 18C. Since the monostable multivibrator 73 is configured to be triggered by the trailing edge of the vertical synchronization signal, the monostable multivibrator 73 generates a pulse in the τ period from t ₁ to t ₂ as shown in FIG. 18D. However, the slice level signal transmitted during this period is sampled and held, and replaced with the old signal. A signal of L ₂ =0.45 volts, for example, determined by the slice level signal immediately after the vertical synchronization pulse in this way is input as the reference slice level L ₂ of the first comparator 69 . The other input of the first comparator 69 is as shown in FIG.
waveform is given and the data level is approximately 0.6 volts, so the reference slice level L ₂ of 0.45 volts is given.
, the address signal and data signal are at the standard slice level L ₂
When it is larger, a high level output is obtained, and when it is smaller, a low level output is obtained. At this time, the reference slice level _L2 is not determined based on the synchronization or data signal on the playback side, but is determined based on the pre-recorded reference slice level signal 38, so it can be set in the middle of the data signal. This makes it easier to read data accurately. FIG. 19 shows the relationship between slice level variation and data reading. When the reference slice level L ₂ is located approximately at the center of the data waveform shown in FIG. 19A as shown by the solid line, the comparator 69 The output also becomes like the solid line in FIG. 19B, and when the signal is a repetition of "1" and "0", it becomes a waveform with a duty ratio of 50%. and the read clock signal is the first
Of course, it can be read in the case shown by the solid line in FIG. 9C, and it is also possible to read even if the clock signal deviates as shown by the dotted line. On the other hand, if the slice level is determined using the conventional method, the ratio of the data and synchronization signal in the reproduced waveform changes due to the drop between the base and emitter of the transistor circuit, and the slice level is set approximately at the center of the data. If this is not possible and the slice level L ₂ ' occurs at the position indicated by the dotted line in FIG. 19A, then the comparator 6
The output of 9 becomes the waveform shown by the dotted line in Figure 19B,
If the clock signal deviates as shown by the dotted line in Figure 19C, it will be impossible to read the data.

Returning to the explanation of FIG. 17 again, the output of the sample and hold circuit 72 is also coupled to the 1.77 times circuit 76,
By multiplying by 1.77, a slice level L ₃ =0.8 volt of the white level signal 40 shown in FIG. As a result, only the white level signal is detected from the third comparator 71. This white level signal is used to determine whether the field is an odd field or an even field and to determine a vertical blanking period.

Next, the resynchronization type write address circuit 52 shown in FIG. 20 will be explained. An address signal+data signal obtained from the separation circuit 50 is sent to the input line 77. That is, the first comparator 69 in FIG.
The output of is sent. This line 77 is coupled to the input terminal of a 4-bit shift register 78, so that the shift register 78 outputs a signal corresponding to a 4-bit address signal. That is, the timing pulse generator 79 generates a timing pulse based on the output of the reference oscillator 9, and when this timing pulse is applied to the clock terminal of the shift register 78, the first clock after the horizontal synchronization pulse The first bit of the address signal is read, the second bit of the address signal is read on the second clock, and the third and fourth bits are read on the third and fourth clocks. The address signal read into the shift register 78 is sent to a holding circuit 81 through four output lines 80, where it is temporarily held. Also, a first digital comparator 82, a second digital comparator 83, and a preset counter 8 for generating a resynchronization address signal.
A detection address signal is also sent to 4.

Line 84' is for transmitting the synchronization signal from separation circuit 50 and is connected to second comparator 7 in FIG.
0 output. this line 8
The synchronizing signal obtained at 4' is differentiated by a differentiating circuit 85, and is inputted to an AND gate 86 and also inputted to a monostable multivibrator 87 as a trigger signal. The monostable multivibrator 87 has τ=
is set to 0.98H, and its output is AND gate 86
Since it is the other input of the AND gate 86, noise is removed from the AND gate 86, and a pulse synchronized with the synchronization signal is generated, and the latch, that is, the holding circuit 8
Control 1. The holding circuit 81 is an AND gate 8
A horizontal address signal is stored every time a pulse is received from 6. +1 circuit 88 for the output of the holding circuit 81
is provided, and 1 is higher than the held address signal.
A larger address signal is output, and this is the first address signal.
input to the digital comparator 82.

The first digital comparator 82 is connected to the shift register 7
Digitally compares the 4-bit address signal currently generated from 8 and the address signal generated 1H ago from the shift register 78 plus the +1 circuit, and if they match, sends out a high level output. . If editing or dropout causes a jump in the time axis and a drop in the horizontal address signal occurs, it becomes impossible to obtain a matching output from the first digital comparator 82.

Line 89 is a white level signal transmission line,
It is coupled to the output of the third comparator 71 in FIG. When the white level signal on line 89 is passed through a low-pass filter 90, it becomes possible to obtain a signal corresponding to the vertical blanking period. During this period, the counter 84 is reset and starts counting from the end of the vertical blanking period. . That is, counting is started based on the synchronization signal generated in the data section _T4 of FIG. 12A. For this purpose, the output of AND gate 86 is coupled to clock terminal CK. When the synchronization pulse is received from the AND gate 86, the counter 84 outputs [0000],
A count output is generated in the 4-bit format of [0001] and becomes the input to the second digital comparator 83. The line 91 is also used as a write address signal for the memory 51. Note that since the output of the counter 84 alone is insufficient for the write address signal of the memory 51, the output of the timing pulse generator 79 is also used. By the way, if the address signal is not missing due to editing etc., the number of horizontal scanning periods (H number) counted by the counter 84 should match the address signal detected by the shift register 78, so the second A high level coincidence output is obtained from the digital comparator 83. This high level signal is then inverted by an inverter 92 to become a low level signal, which becomes an input to an AND gate 93.
The AND gate 93 includes a first digital comparator 82
Since the high level output of is also input, its output becomes low level and the shift register 94 coupled to the output of AND gate 93 does not operate. Therefore,
The three output lines of the shift register 94 are at low level, and the three output lines are connected to the AND
The output of gate 95 is also at a low level. For this reason,
No signal is applied to the preset terminal _L0 of the counter 84, and the counter 84 continues to count the synchronization pulses applied to the clock terminal CK, regardless of the output of the shift register 78.

However, due to editing in the range of 9H to 15H in the data section of FIG. 12A, for example, 1H
If missing, the inputs of the first digital comparator 82 will no longer match, and the output of this comparator 82 will be at a low level. However, 1H after the 1H time axis jump, that is, the missing portion has passed (2H after the time axis jump start point), both inputs of the comparator 82 match again, so its output becomes high level. In contrast, the second digital comparator 8
Both inputs of No. 3 become inconsistent from the start point of the time axis jump due to the missing 1H, their outputs become low level, and the output of inverter 92 becomes high level. This state continues until the output of counter 84 is corrected. For this reason, the first digital comparator 82
The output of the AND gate 93 becomes high level from the moment when the output of If the output of the AND gate 93 is kept at a high level during the period (3H) during which the clock pulse is input, the shift register 94
All three output lines become high level,
A high level signal is generated from the AND gate 95, which is applied to the preset terminal _L0 , and the counter 8
4 is set in the address signal applied from the output line 80 of the shift register 78 to its input terminal IN, and counting continues with this set address signal. Therefore, a correct address signal corresponding to the data is generated from line 91,
Data is written in synchronization with this address signal. When counter 84 is preset and starts operating, both inputs of comparator 83 also match and its output goes high, and the output of AND gate 93 is inverted to low. In the end, if 1H is missing, the address becomes normal after 5H. If 1H is missing due to editing, the point before the 1H missing point
Since the CRC code is different from the CRC code after the 1H missing point, the CRC check circuit 55 naturally determines that the data is error data, and the data from the vertical blanking period to the time of resynchronization is not used. Furthermore, if 1H is missing due to dropout, an incorrect address has been specified in, for example, 5H from the time of the dropout to the time of resynchronization, so it will naturally become error data, and the subsequent CRC check circuit 55 will judge it as an error. Not used.

As mentioned above, in this method, the address signal is detected along with the data from the magnetic tape on which the horizontal address signal is recorded, and the time axis jump is also detected. When a time axis jump occurs, memory writing is performed in synchronization with the address signal. Therefore, even if a time axis jump occurs due to editing or the like, signal processing can be performed without synchronization disturbance. Further, since the preset counter 84 is used and resynchronization is performed by presetting using an address signal, it is relatively easy to achieve resynchronization. Further, since the time axis jump is detected by inputting the current address signal and a signal obtained by adding 1H to the address signal 1H before the current address signal to the comparator 82, the time axis jump can be detected accurately and easily.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-mentioned embodiment.
It is also deformable. For example, Figure 12A
A television format PCM signal as shown in FIGS. and B may be sent via radio waves, received and recorded on a VTR. Further, in the embodiment, a vertical parity bit is added first to form the F row, and a CRC code is also attached to the F row, but the CRC code may be attached first and then the vertical parity bit. In this case, _1F5 in FIG. 8 becomes the vertical parity bit. In this case, the reproduction system first performs a CRC check, and then performs a vertical parity check. Furthermore, after correcting errors based on the CRC check and vertical parity check, the CRC check may be performed again, and if an error occurs, the error data may be corrected by interpolation or previous value holding.

Furthermore, errors due to dropouts may be reduced by recording the same data twice.

[Brief explanation of drawings]

The drawings show a PCM recording and reproducing method according to an embodiment of the present invention, in which Fig. 1 is a block diagram of a recording device, and Fig. 2 shows an explanatory waveform of an analog signal supplied to the input terminal of Fig. 1. Figure 3 is a waveform diagram illustrating the state in which the analog signal in Figure 2 is sampled and held, and Figure 4 is a waveform diagram showing the analog signal in Figure 1.
FIG. 5 is a time chart that explains the output of the digital converter. FIG. 5 is a time chart that explains the output of the parallel-to-serial converter in FIG. 1. FIG. 6 is the data in the vertical parity memory of FIG. 1. FIG. 7 is a layout diagram explanatory of the data arrangement with vertical parity bits added; FIG. 8 is a layout diagram explanatory of the data arrangement after adding the CRC code; 9 is an explanatory layout diagram showing the data block and the data arrangement therein, FIG. 10 is a time chart explanatory showing the output of the CRC code adding circuit in FIG. 1, and FIG. A time chart that explains the output of the interleaving memory. Figure 12A is a composite PCM of an even field.
Figure 12B is a waveform diagram showing the composite PCM signal of an odd field, Figure 13 is the waveform diagram showing the signal.
FIG. 2 is a waveform diagram showing an enlarged part of A for explanatory purposes. FIG. 14 is a waveform diagram showing an enlarged part of FIG. 13 for explanatory purposes. FIG. Figure 15A is a waveform diagram that explains the input and output of the AGC circuit, and Figure 15B is a waveform diagram that shows changes in waveforms.
15C is a waveform diagram showing the output of the pre-emphasis circuit and the white clip circuit. FIG. 15C is a waveform diagram showing the output of the conventional white clip circuit.
Figure 6 is a block diagram of the playback device, and Figure 17 is the block diagram of the playback device.
Figure 18 is a block diagram showing the separation circuit in Figure 1.
FIG. 7 is a waveform diagram showing the states of points A to D in FIG. 7, FIG. 19 is a waveform diagram showing the relationship between data and the slice level and the relationship with the clock, and FIG. 20 is a block diagram showing the resynchronization type write address circuit. be. In the symbols used in the drawings, 16 is a memory for vertical parity, 17 is a vertical parity bit addition circuit, 18 is a memory for CRC, and 19 is a CRC.
Code addition circuit, 20 is memory for interleaving, 2
3 is a resynchronization signal generation circuit, 25 is a white level signal generation circuit, 27 is a data slice level generation circuit,
28 is a VTR, 29 is an AGC circuit, 30 is a pre-emphasis circuit, 31 is a clamp/white clip circuit, 38 is a slice level signal, 39 is a data signal, 40 is a white level signal, 41 is a horizontal synchronization pulse, 42 is for resynchronization 43 is a white level signal, 50 is a separation circuit, 52 is a resynchronized write address circuit, 54 is a memory for deinterleaving, 55 is a CRC check circuit, 56 is a memory for vertical parity check, 57 is a vertical parity check circuit. 58 is an error correction circuit; and 60 is a correction circuit.

Claims (1)

[Claims] 1. Transmitting a composite PCM signal in a television signal format including a PCM signal, a synchronization signal, and a slice level signal having an amplitude approximately half of the amplitude of the PCM signal, and transmitting the transmitted composite PCM signal. 1. A PCM signal processing method, comprising extracting and holding the slice level signal from a PCM signal, and slicing the PCM signal according to the held slice level.