JPH0158524B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output device for a programmable controller, and in particular, to combine input circuits or output circuits into one channel for each fixed number of circuits, and to combine multiple types of input circuits with different numbers of installed channels. Or, in a programmable controller which forms an output card and is further provided with an input/output rack for connecting a certain number of these input or output cards, while driving the input circuit or output circuit in units of channels, each channel This invention relates to an input/output device for a programmable controller that allows access to cards and input/output racks using an address bus with a minimum number of bits.

An input/output address space having a width of 2 K bits is divided into multiple channels consisting of addresses of 2 L bits per channel, and input or output circuits are divided from the number of 2 L circuits per channel. A plurality of types of input or output cards each having a different number of installed channels are provided, each having a number of channels equal to 2 to the Z power (Z is a plurality of different integers), and furthermore, 2 to the N power to which the input or output cards can be connected. In a programmable controller with multiple input/output racks each having 1 card connector, if you want to access each input or output circuit in units of 1 channel, any number of channels can be installed for each card connector. In order to configure the card to be connectable, three dedicated address buses are usually required, each corresponding to an input/output rack address, an input/output card address, and a channel address.

However, when three address buses are provided in this way, the maximum number of digits for each address line is determined according to the maximum number of racks, the maximum number of cards, and the maximum number of channels, so it does not correspond to the actual input/output circuit. Although it is sufficient for the address space to be as wide as 2 to the K power, there is a large amount of wasted address space, resulting in an extremely uneconomical design.

Also, if you divide the input or output circuit into channels, cards, and racks in this way, and attempt to configure the input/output circuit for each rack so that it can be installed at any location, each channel will be fixed ( It is possible to identify each card by assigning a fixed (absolute) address within the rack, but each rack has an address based on the total number of racks and the arrangement of each rack. changes, so
It is not possible to attach a fixed address as mentioned above,
Therefore, it is necessary to provide an address setting device that can be changed according to the user's specifications. For this reason, conventional PCs of this type have had the problem that input or output data is often transferred to the wrong rack due to setting errors in the address setting device, resulting in unexpected malfunctions.

This invention was made in order to solve the above-mentioned problem, and its purpose is to provide multiple types of connectors with different numbers of installed channels to each connector provided in the input/output rack in this type of input/output device. While the configuration allows for selective connection of any input or output card, the channel of each card can be accessed using an address bus with the minimum number of bits, and each input/output rack can be connected to the CPU. By connecting the racks in a fixed order in a sequential manner, it is possible to allocate a unique address to each rack without providing any special address setting means.

In order to achieve the above object, this invention
The necessary high-order digits of the address bus leading to the CPU are connected in a flexible manner through an arithmetic circuit provided in each rack, and each rack is provided with an arithmetic data switch and setter, and furthermore, the arithmetic results of the arithmetic means are By providing a digital multi-comparator that compares the size based on predetermined reference data, it is possible to assign a unique address to each rack, and on the other hand, the weighting of the common line for card identification of each card connector is determined by the digital multi-comparator. By providing a line selector that switches based on the output, each channel of each card can be accessed using an address bus with a minimum number of bits.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As shown in Figure 1, the basic system configuration of a PC includes an input circuit 1 for receiving input signals from external sensors, an output circuit 2 for driving external load equipment, and a memory for storing user programs. The user program memory 3 and the input data taken in from the input circuit 1 are written to a predetermined input area in the input/output memory 4, and the data is stored in the program memory 3 based on the written input data. It consists of a CPU 5 that sequentially executes user commands, rewrites a predetermined output area of the input/output memory 4 with the execution results, and transfers the rewritten data to the output circuit 2, and a working memory. 6 is used as a working area during calculations in the CPU 5, and a system program that defines the operation of the CPU 5 is stored in a system program memory 7.

As shown in FIG. 2, the input/output area in the input/output memory 4 has a storage area with a width of 2 to the 9th power (=512) bits that can be allocated to one input or output circuit. It is provided,
In particular, in this example, each word has a word structure of 2 to the power of 2 (9-3) (=64) consisting of 2 to the power of 2 (=8) bits.

Next, the input/output address space, which has a width of 2 to the 9th power (=512) bits and is allocated to each input circuit or output circuit, is made up of 2 to the 3 power of 2 (=8) addresses for one channel. Each input or output card has two input or output circuits.
0th power (=1) or 2 to the 2nd power (=4) channels (one channel has 2 to the 3rd power (=8) number of circuits)
This reduces the number of installed channels to 1.
Two types of input or output cards are available:

These input or output cards are installed in the input/output rack described later.
It is configured so that it can be connected to multiple card connectors.

Next, the PC according to this embodiment includes the user program memory 3, the input/output memory 4, the CPU 5,
A CPU unit (not shown) that integrally accommodates working memory 6 and system program memory 7
and a plurality of input/output racks #0 to #4. In each input/output rack, 2 to the power of 3 (=8) input or output cards are removably attached, and in this example, as shown in FIG. Two to the third power (=8) cards for square (=4) channels are attached, and on the other hand, in racks #0, #2 to #4, there are cards for 2 to the third power (=8).
The card for the power (=1) channel is 2 to the power of 3 (=
8) Attached.

Next, FIG. 4 is a block diagram showing the electrical configuration of the interface provided in each input/output rack. In the figure, address data input terminals T3 to T5 are connected to address data output terminals 9-3 (=6) of the aforementioned CPU unit when the rack is used as a first-stage rack.
The top three A00 to A05 address lines of the book
03 to A05, and when the rack is used as a rack in the next stage or later, the address data sending terminals T3' to T3 of each previous stage rack are connected to
5'.

The numerical value setter 8 is configured to be able to switch and set one of the numerical values 2 to the 0th power (=1) and 2 to the 2nd power (=4) corresponding to the number of installed channels of each card.

The arithmetic circuit 9 has the address data input terminal T.
The configuration is such that the numerical value set by the numerical value setting device 8 is added to the address numerical data input from T3 to T5. The digital multi-comparator 10 converts the numerical data corresponding to the calculation result of the calculation circuit 9 into two sets corresponding to the set numerical value 2 in the numerical value setter 8 to the 0th power (=1) and the squared power of 2 (=4). The numerical data 2 to the 0th power (=1) and 2 to the 2nd power (=4) are compared in magnitude, and if the comparison result is smaller than 2 to the 0th power, "0" is output to line 11, and the other If it is smaller than 2 squared (=4), "0" is output to line 12.

Address data output terminals T3' to T5' output numerical data corresponding to the calculation results of the calculation circuit 9.
Used to send to the subsequent I/O rack.

The lower address data input terminals T0 to T2 are connected to the address line A00 leading to the CPU unit.
~A05, it is connected to the lower 3 bits A00~A02.

The line selector circuit 13 selects from among the 9-3 (=6) address lines output from the CPU unit the set value 2 in the value setter 8 to the Z power (Z=0 or 2) and each of the above. N lines corresponding to the number of connectors in the rack (2) to the Nth power (N=3) (second Z-th bit, second (Z+1)-th power bit, ... second (Z+N-1)-th power bit) is configured to selectively output. For example, if 2 to the 0th power (=1) is set in the numerical setting device 8 and the number of connectors in the rack is 2 to the 3rd power (=8), the terminals Y1 to Y3 of the line selector circuit 13 are , three lines (second 0th power bit A00, second 1st power bit A01, second power bit A02) are output, and on the other hand, the numerical value set in the numerical value setting device 8 is 2 to the 2nd power. (=
4), and the number of connectors is 2 to the 3rd power (=8)
In this case, three bit lines (second square bit A02, second third bit line
The power bit A03 and the second power bit A04) are output.

1 card 1 channel selection circuit 14 selects address lines A00 and A01 when the value setter 8 is set to the square of 2 (=4).
The output of this one card one channel selection circuit is input to the terminal A4 of the line selector circuit 13.

On the other hand, terminals B4 and B of the line selector circuit 13
5, the 2 to the 0th power (=1) output of the digital multi-comparator 10 is inputted, and furthermore, the 2 to the 0th power (=4) output of the digital multi-comparator 10 is input to the terminal A5 of the same line selector circuit 13. It has been entered.

Therefore, the value setter 8 uses 2 to the 0th power (=
1) When "0" is input to the terminal S of the line selector circuit 13, the B input side is selected in the line selector circuit 13,
2 to the power of 0 (=1) output from the digital multi-comparator 10 appears at the output terminals Y4 and Y5, respectively.

On the other hand, when "1" is input to the terminal S of the line selector circuit 13 due to the setting of the square of 2 (=4) in the numerical value setter 8, the A input is input to the line selector circuit 13. selected, the output of the 1 card 1 channel detection circuit 14 appears at the output terminal Y4, and the 2 squared (=
4) Output will appear.

Next, lower address data input terminals T0, T
1 and each output terminal Y1 of the line selector circuit 13
~Y5 connects each card connector C0 via a conductive pattern on the motherboard fixed in the rack.
~C7 is connected to the corresponding terminal.

Connector specific address output terminals CS0 to CS2 of each card connector C0 to C7 are configured to output data indicating a specific (absolute) address within the connector rack.

Channel address output terminal DAB0, DAB1
is connected to the lower two bit lines (second 0th power bit A00, second 1st power bit A01) among the six address lines that lead directly to the address data sending terminal of the CPU. It is configured to output data indicating the unique address within the card of each channel.

Connector specified address output terminal AB0~AB2
are connected to three lines output from terminals Y1 to Y3 of the line selector circuit 13, and are configured to output data indicating a unique (absolute) address within the rack corresponding to each connector.

The maximum channel number output terminals AB3 and DAB3 are
Output terminals Y4, Y of the line selector circuit 13
5, and when the value 2 to the 0th power (=1) is set in the numerical value setter 8, a 1 bit indicating that the maximum number of installed channels of the rack concerned is 8 channels is sent to the terminal AB3. When a signal is output and the value 2 squared (=4) is set in the value setter 8, a 1-bit signal is sent to the terminal DAB3 indicating that the maximum number of channels installed in the rack is 32. A signal is output.

On the other hand, if the numerical value setter 8 sets the numerical value 2 to the 0th power (=1), the terminal
DAB3 has the digital multi comparator 1
When 0 to the power of 2 (=1) is output, and on the other hand, the square of 2 (=4) is set in the numerical value setter 8, the terminal AB3 is connected to the 1 card 1 channel selection circuit 14. The output will be output.

Next, Figure 5 is a block diagram of the channel activation control circuit installed in a card for 2 to the 0th power (=1) channel, and Figure 6 is a block diagram of the channel activation control circuit installed to a card for 2 to the 2nd power (=4) channel. FIG. 2 is a block diagram of a channel activation control circuit according to the present invention.

In these drawings, connector-specific address input terminals CS0' to CS2' are configured to be connectable to connector-specific address output terminals CS0 to CS2 of each connector.

Connector specified address input terminal AB0'~AB
2' is configured to be connectable to connector designation address output terminals AB0 to AB2 of each of the connectors.

Channel address input terminal DAB0', DAB
1' is configured to be connectable to channel address output terminals DAB0 and DAB1 of each of the connectors.

Maximum number of channels signal input terminal AB3', DAB
3' are connected to the maximum channel number signal output terminals AB3 and DAB3 of each of the connectors, respectively.

Each output of the E-OR circuit group 15 outputs "1" based on the match between the data of the connector-specific address input terminals CS0' to CS2' and the data of the connector specified address input terminals AB0' to AB2'. , and the AND gate 16 is opened every time "0" arrives at the maximum channel number signal input terminal AB3' or DAB3'.

In the case of a 2 to the 0th power (=1) channel card, this AND gate 16 is used as shown in FIG.
The output becomes an activation signal for the input circuit or output circuit for one channel.

On the other hand, in the case of a card for 2 squared (=4) channels, the output of the AND gate 16 becomes an enable signal for the channel decoder 17, as shown in FIG. The data on the channel address input terminals DAB0' and DAB1' are decoded and output as CH0 to CH3, and these signals become activation signals for the input or output circuits of the respective channels.

In the above configuration, the CPU
Address line A00~ output from the unit
A05 is connected in a flexible manner through each input/output rack #0 to #4, and the numerical value setter is set to the square of 2 (=4) for the #1 rack, and the other racks #0, #2 to #4 are set. For 4 racks, if the value setter is set to 2 to the 0th power (=1), the input circuit or output circuit mounted on each card in each rack will be:
Address assignment is automatically performed individually as shown in FIG.

Next, when address data corresponding to each input circuit or output circuit is sent in negative logic to each address line A00 to A05 of the CPU unit shown in FIG. 3, the address data provided in each rack as shown in FIG. On the output side of the arithmetic circuit 9, 2 to the 0th power (=1) or 2 to the 2nd power (=
4) is output, which causes each rack to detect, via the digital multicomparator, that it is being addressed.

On the other hand, when each rack receives address designation in this way, the line selector circuit 13 is switched and controlled according to the maximum number of installed channels set for the rack, and its output terminals Y1 to Y3 are connected to the rack. Card address data that advances in synchronization with each channel scan in each card is output, and terminals DAB0 and DAB0 of the other card connector are output.
DAB1 is supplied with channel address data for sequentially scanning the channels in each card.

Therefore, as shown in Fig. 3, there are 2 squared (=4) channel cards in the #1 rack.
8) and set the numerical value setting device 8 of the rack to the square of 2 (=4), the input or output circuit of each channel mounted on each card can be sequentially addressed. , input or output data is normally transferred via the data bus 18 shown in FIG.

On the other hand, as shown in FIG.
If you connect 8 cards and set the value setting device of the rack to 2 to the 0 power (=1), only the first channel of each card will be used for actual input or input, as shown in the figure. It will be used as an output circuit, and the remaining three channels of each card can be used as addresses for auxiliary relays. In other words, the area corresponding to the three channels of the input/output memory shown in FIG. 2 can be used as the address for the auxiliary relay.

That is, when setting the value 2 to the 0th power (=1) in rack #0, the line selector circuit 13
Due to the switching action of , terminal DAB3 of connector C0
In the digital multi comparator 10 2 0
Since a multiplied (=1) output is provided, there is no channel scanning within each card, and only the first channel within each card is addressed.

Furthermore, as shown in Figure 9, 0 of 2 is placed in #0 rack.
Multiply (= 1) channel cards to the power of 2 (=
If 8) cards are connected and the numerical value setter 8 of the rack is set to the square of 2 (=4), each card will receive address designation as shown in Figure 9, and in the same way. It becomes possible to use an empty channel as an auxiliary relay area. That is, when the numerical value setter 8 is set to the square of 2 (=4), the output of the 1-card 1-channel selection circuit 14 is supplied to the terminal DAB3 of the connector C0 by the switching action of the line selector circuit 13. As a result, address assignment as shown in FIG. 9 is performed.

Thus, according to the PC related to this example,
By sequentially connecting each input/output rack to the CPU unit and switching the numerical setting device 8 as necessary, each connector in each rack can be set to 2 to the 0th power (=1) or 2 to the power of 2. squared (=4)
No matter which channel card is connected,
Channels within each card can be accessed from the CPU through six address lines, making this type of
To make the configuration of an address bus in a PC extremely simple, and to prevent malfunctions due to address setting errors as in the case where a variable setting device is provided for setting the unique address of each rack. becomes possible.

In the above embodiment, the input/output address space having a width of 2 to the 9th power bit is divided into 2 to 3 bits per channel.
divided into 6 channels, and each channel is equipped with input or output circuits as many as 2 to the 0 power (=1) and 2 to the power of 2 (=4) channels, each consisting of 2 to the 3 power (=8) circuits. A programmable controller is provided with two types of input or output cards having different numbers of installed channels, and further provided with an input/output rack having 2 to the power of 2 (=8) card connectors to which the input or output cards can be connected. Although the input/output device has been described, the present invention is not limited to the above embodiment.

In other words, an input/output address space having a width of 2K bits is divided into 2(K-L) channels each having addresses of 2L bits per channel, and the input or output circuit is divided into 2(K-L) channels having a width of 2K bits. 2 to the Z power (Z
= M1, M2, ...MP) Input or output cards of P types each equipped with a different number of installed channels are provided, and the input or output card has 2 N card connectors to which the input or output cards can be connected. It can be applied to an input/output device of a programmable controller provided with an output rack.

In this case, in each of the input/output racks, if the rack is used as the first stage rack, at least the upper N of the (K-L) address lines leading to the address data output terminal of the CPU are connected to the input/output racks. If the rack is connected and the rack is used as a rack in the next stage or later, the address data input terminal connected to the address data output terminal of each rack and the Z-th power of the numerical value 2 corresponding to the number of channels are connected. a numerical value setter that can be switched and set; a subtraction circuit that adds or subtracts the set value of the numerical value setter to or from the address data input from the address data input terminal; and a subtraction circuit that corresponds to the calculation result of the calculation circuit. a digital multi-comparator that compares the numerical data set in the numerical value setter with specific numerical data corresponding to the Z power of the set numerical value 2, and outputs the comparison result to the corresponding terminal corresponding to the set numerical value; and the arithmetic circuit. an address data output terminal for sending numerical data corresponding to the calculation result to the subsequent input/output rack;
Among the (K-L) address lines output from the CPU, N bit lines (second Z-th power) corresponding to the Z power of the set value 2 in the numerical value setter and the N power of the number of connectors 2 are selected. , 2 (Z+
1) A line selector circuit or the like may be provided for selectively outputting the power bit, . . . the second (Z+N-1) power bit.

Furthermore, in this case, each card connector provided in the input/output rack has a connector-specific address output terminal that outputs data indicating the unique address within the rack of the connector, and a connector-specific address output terminal that leads to the address data output terminal of the CPU (K-L). ) address lines, the lower at least P (however, 2 to the MP power is the maximum number of channels) lines (second 0th power bit, second 1st power bit... second (P-1 ) a channel address output terminal that is connected to the N bit lines and outputs data indicating a unique address in the card for each channel; and a rack that is output from the line selector circuit and connected to the N bit lines and corresponds to each connector. The connector is connected to the connector designated address output terminal that outputs data indicating the unique address in the rack, and to each output line of the digital multi-comparator, and the maximum number of installed channels of the rack is N x (2 to the power of M1), N x (2 M2 of
. . N×(2 to the power of MP).

Furthermore, each input or output card has a connector specific address input terminal connectable to the connector specific address output terminal, a connector specified address input terminal connectable to the connector specified address output terminal, and the channel address output terminal. Among the constituent bit lines, a channel address input terminal that can be connected to one or more bits corresponding to the number of channels installed on the card, and among the maximum channel number signal output terminals, the number of channels installed on the card. Input or output of the corresponding channel based on the maximum number of channels signal input terminal that can be connected to the terminal corresponding to the terminal, the connector-specific address data, the connector specified address data, the channel address data, and the maximum number of channels signal. An activation control circuit for activating the circuit may be provided.

As is clear from the description of the embodiments above, according to the present invention, it is possible to greatly improve the degree of freedom in system configuration on the manufacturer's side in this type of PC, and it is also possible for the user to avoid errors in setting the rack address. This makes it possible to prevent malfunctions caused by such factors, significantly improving the functionality and reliability of this type of PC, and reducing costs.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the basic system configuration of a PC, Figure 2 is a memory map showing the input/output memory configuration, and Figure 3 is the connection relationship between input/output racks and the contents of the cards connected to each rack. 4 is a block diagram showing the electrical configuration of the interface in the input/output rack. FIG. 5 is a block diagram showing the configuration of the channel activation circuit for a 1-channel card. The figure is a block diagram showing the configuration of a channel activation circuit for a 4-channel card, Figure 7 is a diagram showing the relationship between address data and the output of each arithmetic circuit, and Figure 8 is a diagram showing the relationship between address data and the output of each arithmetic circuit. FIG. 9 is a diagram showing address allocation when 8 channels are mounted on a 32-channel rack. 1... Input circuit, 2... Output circuit, 3... User program memory, 4... Input/output memory, 5...
...CPU, 6... Working memory, 7... System program memory, 8... Numerical setting device, 9...
...Arithmetic circuit, 10...Digital multi-comparator, 11...2 to the 0th power bit output line, 12...
...2 squared bit output line, 13... Line selector circuit, 14... 1 card 1 channel selection circuit, 15... EOR circuit group, 16... AND gate, 17... Channel decoder, 18... Data bus , T0-T2...lower address data input terminals, T3-T5...address data input terminals, T3'-T5'...address data output terminals,
A00-A05...Address line leading to CPU, C0-C7...Card connector, CS0-SC
2...Channel address output terminal, AB0~
AB2……Connector specified address output terminal, AB
3, DAB3...Maximum channel number output terminal, CS
0'~CS2'...Connector specific address input terminal,
AB0' to AB2'...Connector specification address input terminals, DAB0', DAB1'...Channel address input terminals, AB3', DAB3'...Maximum channel number signal input terminals.

Claims (1)

[Scope of Claims] An input/output address space having a width of 12 K bits is divided into multiple channels each consisting of an address of 2 L bits per channel, and an input or output circuit is arranged per channel. A plurality of types of input or output cards each having a different number of installed channels each having a number of 2 to the power of Z (Z is a plurality of different integers) channels each having a number of circuits of 2 to the power of L are provided, and furthermore, the input or output card is An input/output device for a programmable controller having a plurality of input/output racks each having connectable card connectors to the power of 2; If
If the rack is connected to at least the upper N of the (K-L) address lines output from the CPU, and the rack is used as a rack in the next stage or later, the K-L addresses of each previous stage rack are connected. K-L address data input terminals connected to the data transmission terminal; a numerical value setter capable of selectively setting one of the numerical values corresponding to each of the channel numbers Z; and from the address data input terminal. an arithmetic circuit that adds or subtracts a numerical value set by the numerical value setter to input address numerical data; and a numerical data corresponding to the calculation result of the arithmetic circuit, which is set to the Z power of the numerical value 2 set in the numerical value setter. A digital multi-comparator that compares the size with specific numerical data corresponding to the set value and outputs the comparison result to the corresponding terminal corresponding to each set numerical value, and a digital multi-comparator that outputs the comparison result to the corresponding terminal corresponding to each set value, and a subsequent input/output rack that outputs the numerical data corresponding to the calculation result of the arithmetic circuit. K-L for sending to
From the address data output terminal of the book and the K-L address lines output from the CPU, set the numerical value in the numerical setting device (2 to the Z power) and the number of connectors (2 to the N power).
N lines defined by (second Z-th power bit, second Z+1-th power bit, ... second Z+N
-1 power bit); Each card connector provided in the input/output rack is provided with a connector-specific address output terminal that outputs data indicating the unique address of the connector in the rack. , K- leading to the address data sending terminal of the CPU
Among L address lines, at least P
(where 2 to the power of P is the maximum number of channels of the input/output card)
a channel address output terminal that is connected to the second P-1 power bit) and outputs data indicating the unique address in the card of each channel, and a channel address output terminal that is connected to the N lines ( a connector address output terminal connected to the second Z bit, second Z+1 bit, ... second Z+N-1 bit) and outputting data indicating the in-rack unique address of each connector; A 1-bit signal that is connected to each output line of the digital multi-comparator and indicates which one of (2 to the power of Z) x N (where Z is an integer) is the maximum number of channels that can be installed in the rack. A plurality of maximum channel number output terminals are provided; each input or output card is provided with a connector-specific address input terminal connectable to the connector-specific address output terminal; and a connector-specific address input terminal connectable to the connector address output terminal. a connector designation address input terminal; a channel address input terminal connectable to one or more bits corresponding to the number of installed channels of the card among the bit lines forming the channel address output terminal; and the maximum number of channels. Among the signal output terminals, the maximum number of channels signal input terminal that can be connected to the terminal corresponding to the number of installed channels of the card, the connector-specific address data, the connector specified address data, the channel address data, and the maximum number of channels. an activation control circuit for activating the input or output circuit of the corresponding channel based on the signal; and connecting each of the input/output racks in sequence through each address data input terminal and output terminal. At the same time, by connecting the address data input terminal of the first stage rack to the address data output terminal of the CPU, and setting an appropriate value in the numerical value setter of each rack, any rack constituting the address space of 2 K bits can be created. CPU with K-L address lines on any channel of any card.
An input/output device for a programmable controller, characterized in that it can be accessed from.