JPH0158528B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is effective for timing pulse generation circuits, particularly machine cycle generation circuits of microcomputers (hereinafter referred to as microcomputers), and relates to timing pulse generation circuits in which the timing pulse generation order can be changed.

In general, instructions used in microcomputers do not have a fixed word length, but include 1-byte instructions, 2-byte instructions, etc., and execution of the instructions is completed after passing through several machine cycles, which are the execution unit of data processing. Since the number of machine cycles is not uniform depending on each instruction, the information processing device proposed in Application No. 55-92542 is configured to execute similar data processing in the same machine cycle. It is known to complete execution of an instruction by generating only a cycle signal. In these cases, the machine cycles are generated in the following order: an operation code fetch cycle for decoding an instruction, a memory read cycle, an operation cycle, and a memory write cycle. However, this order is not uniform depending on the instruction, and there are instructions that require a memory read cycle after an operation cycle, such as an instruction such as index addressing that determines a memory address based on the address operation result. Conventionally, the following methods have been used to implement this type of command.

The first is a method in which a memory read cycle is also provided after an arithmetic cycle, and the second is a method in which a memory read is executed in a memory write cycle after an arithmetic cycle. However, the first
The above method requires an extra memory read cycle generation circuit, resulting in an increase in hardware.
In addition, in the second method, memory reads are controlled using machine cycle signals, which are originally memory write cycles, which requires transferring the machine cycle signals to various control systems and requiring extra control circuits. The drawback was that it required an increase in wiring and hardware.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a timing pulse generation circuit that has a simple circuit configuration and can be used in a machine cycle counter that is particularly effective in executing instructions of a microcomputer.

The timing pulse generation circuit according to the present invention includes first and second flip-flops that are set by a timing pulse generation request signal, and a first OR gate that receives the inverted output of the second flip-flop and a generation order instruction signal. means, first AND gate means for receiving a non-inverting output of said first flip-flop and an output of said first OR gate means and generating a first timing pulse; means for resetting the first flip-flop; second OR gate means for receiving the inverted output of the first flip-flop and the inverted signal of the sequential instruction signal; The second AND gate means receives the outputs of the two OR gate means and generates a second timing pulse, and means resets the second flip-flop with the second timing pulse.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit connection diagram illustrating an embodiment of the present invention, and reference numerals 11 to 13 are set-reset type flip-flops (hereinafter abbreviated as F/F) which output signals in synchronization with a clock φ. 14 and 15 are OR gates, and 16 to 19 are AND gates. C
11 is a timing generation order change request signal;
C12-C14 are generation request signals for timing signals M2-M4. 2 and 3 are time charts for explaining the operation of FIG. 1. First, the operation of the circuit shown in FIG. 1 will be explained using FIG. Timing generation request signals C12 to C14 are M
When the logic becomes "1" (hereinafter simply referred to as "1") at the timing of 1, F/Fs 11 to 13 are set, and in synchronization with clock φ, the Q output becomes "1" and the output becomes "0".
(hereinafter simply referred to as "0"). Here, since the timing generation order change request signal C11 is "0", the OR gate 14 becomes "1", and the timing signal M2 is output next to the timing signal M1. While the timing signal M2 is being output, the output of the F/F 11 is "0", so all other timing signals are "0". On the other hand, since M2 is input to the reset input of F/F11, the timing signal M2 is "1".
Then, the Q output becomes "0" and the output becomes "1" in synchronization with the next clock φ, and M3 is output. Similarly, M4 is output, and when all F/Fs are reset, M1 is output. As mentioned above, the timing generation order is M1, M2, M3, M4, M1
becomes. Next, explanation will be given using the time chart shown in FIG. Timing generation request signals C12 and C1
3 becomes "1" at the timing of M1, F/F11 and F/F12 are set, and Q is synchronized with clock φ.
The output is “1” and the output is “0”. Here, since the timing generation order change request signal C11 is "1", the OR gate 15 becomes "1", and the timing signal M3 is output next to the timing signal M1. Furthermore, during the period of timing M3, since the OR gate 14 is "0", M2 remains "0". Next, when the timing signal M3 becomes "1", the Q output becomes "0" and the output becomes "1" in synchronization with the next clock φ.
M2 is output. Since F/F13 has not been reset, timing signal M4 is not output, and M2
Next, M1 is output. As described above, the timing generation order is M1, M3, M2, M1, and M
The order of occurrence of 2 and M3 is changed.

When using this invention as a machine cycle counter for an information processing device such as a microcomputer, M1 to M4
correspond to the opcode fetch cycle, memory read cycle, arithmetic cycle, and memory write cycle, respectively. By allocating in this manner, for example, in the case of an instruction to transfer the result of an operation between the contents of the memory and the contents of a general-purpose register to the memory, timing signals are generated in the order of M1 to M4. Furthermore, in the case of an instruction that involves address operation such as index addressing, the order of occurrence of memory read cycle M2 and operation cycle M3 can be changed, so an extra memory read cycle is required between operation cycle M3 and memory write cycle M4. There is no need to provide hardware for generation, and M4, which was originally assigned to the memory write cycle,
This is very effective because it eliminates the need for a control circuit that performs memory reads at timing and for wiring machine cycle signals to the control circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation of the circuit shown in FIG. 11-13...Flip-flop, 14,15
...Or Gate, 16-19...And Gate,
C11 to C14...control signal, φ...clock.

Claims (1)

[Claims] 1 first and second flip-flops set by a timing pulse generation request signal;
a first OR gate means receiving the inverted output of the second flip-flop and instruction signals in the order of generation; and a first OR gate means receiving the non-inverting output of the first flip-flop and the output of the first OR gate means; first AND gate means for generating a pulse; and means for resetting the first flip-flop with the first timing pulse;
second OR gate means receiving an inverted output of the first flip-flop and an inverted signal of the sequential instruction signal; and a non-inverting output of the second flip-flop and an output of the second OR gate means. A timing pulse generating circuit comprising: second AND gate means for generating a second timing pulse; and means for resetting the second flip-flop with the second timing pulse.