JPH0158878B2 - - Google Patents
Info
- Publication number
- JPH0158878B2 JPH0158878B2 JP59120204A JP12020484A JPH0158878B2 JP H0158878 B2 JPH0158878 B2 JP H0158878B2 JP 59120204 A JP59120204 A JP 59120204A JP 12020484 A JP12020484 A JP 12020484A JP H0158878 B2 JPH0158878 B2 JP H0158878B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- holder
- plating
- copper
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、微細パターンを容易に得ることがで
きる配線板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a wiring board that allows a fine pattern to be easily obtained.
(従来の技術)
配線板の線幅、線間隔はLSIの高集積化にとも
ないますます細くなつている。しかし、従来の製
造方法では例えば、銅張積層板をエツチングして
パターンを形成する場合、100μm以下が加工限
界であり、これ以下の線幅では断線やシヨートが
発生し易くなる。これは銅張積層板の製造工程に
おいて発生するへこみ、きずなどが原因である。
また線図、線間隔が50μm位になると銅張積層板
表面の微少な凹凸やうねりにより線幅精度が低下
する。また、このような銅張積層板に通常使用さ
れている銅箔が18〜35μmであり、スルーホール
を形成するために行うめつきによつて最外層の導
体の厚さは50〜70μmになるため線幅が100μm以
下ではエツチングの適切な条件をみいだすことが
困難である。ここで、銅張積層板に5〜9μmの
厚さの銅箔を使用すれば、内層回路のようにその
銅箔の上に導体を形成する必要のない箇所は、精
度よくエツチングできるようになるが、最外層は
スルーホールを形成するために行うめつきによつ
てその導体の厚さは30〜40μmになり、やはり線
幅が100μm以下のエツチングは困難である。(Conventional technology) The line width and line spacing of wiring boards are becoming thinner and thinner as LSIs become more highly integrated. However, in conventional manufacturing methods, for example, when forming a pattern by etching a copper-clad laminate, the processing limit is 100 μm or less, and line widths smaller than this are likely to cause wire breaks and shorts. This is caused by dents, scratches, etc. that occur during the manufacturing process of copper-clad laminates.
Furthermore, when the line spacing becomes about 50 μm, the line width accuracy decreases due to minute irregularities and waviness on the surface of the copper-clad laminate. In addition, the copper foil normally used for such copper-clad laminates is 18 to 35 μm thick, and the thickness of the outermost conductor layer is 50 to 70 μm depending on the plating performed to form the through holes. Therefore, it is difficult to find suitable conditions for etching when the line width is less than 100 μm. If a copper foil with a thickness of 5 to 9 μm is used for the copper-clad laminate, parts such as inner layer circuits where there is no need to form conductors on the copper foil can be etched with high precision. However, the outermost layer has a conductor thickness of 30 to 40 .mu.m due to plating performed to form through holes, and etching with a line width of 100 .mu.m or less is difficult.
このような事から、エツチング法ではなく、必
要な部分にめつきにより回路を形成するアデイテ
イブ法が微細パターンの形成に適するが、現状で
は基板表面の粗さが大きく、また不必要な場所に
もめつき金属が析出する銅ふり現象があり、エツ
チングにより回路の形成を行うサブトラクト法以
上の微細なパターンの形成ができない。 For these reasons, the additive method, in which circuits are formed by plating in the necessary areas, rather than the etching method, is suitable for forming fine patterns, but at present the surface of the substrate is very rough, and unnecessary areas are left unattended. There is a copper splatter phenomenon in which attached metal precipitates, and it is not possible to form finer patterns than the subtract method, which forms circuits by etching.
また、5〜9μmの厚さの銅箔を用いた銅張積
層板の必要な部分にのみめつきを行つた後、クイ
ツクエツチを行つて、不要な部分の銅箔のみを除
去するセミアデイテイブ法においても、前記の厚
い銅箔を用いた銅張積層板と同様に、銅張積層板
自体の欠陥や特性に支配され、80μm以下の微細
パターンの形成は困難である。 In addition, a semi-additive method can be used in which the necessary parts of a copper-clad laminate using copper foil with a thickness of 5 to 9 μm are marked, and then a quick query is performed to remove only the unnecessary parts of the copper foil. Similar to the copper-clad laminate using thick copper foil, it is difficult to form a fine pattern of 80 μm or less because it is dominated by the defects and characteristics of the copper-clad laminate itself.
そこで、近年では、導電性を有する保持体2の
表面に所望の形状にめつきレジスト1を形成し、
該保持体2の除去条件と異なる金属層と他の金属
層とからなる金属層4をめつきにより形成し、前
記めつきレジスト1を除去し、前記金属層4の面
に絶縁基材を重ね合わせ圧着し、前記金属層4が
露出するまで前記保持体2を除去するという導体
回路を埋め込む配線板の製造法が多用されるよう
になつてきた。 Therefore, in recent years, a plating resist 1 is formed in a desired shape on the surface of a conductive holder 2.
A metal layer 4 consisting of a metal layer and another metal layer different from the removal conditions of the holder 2 is formed by plating, the plating resist 1 is removed, and an insulating base material is overlaid on the surface of the metal layer 4. A method of manufacturing wiring boards in which conductor circuits are embedded, which involves pressing together and removing the holder 2 until the metal layer 4 is exposed, has come into widespread use.
(発明が解決しようとする課題)
しかし、この従来の導体回路を埋め込む配線板
の製造法によつて得られた配線板は微細な配線パ
ターンを形成することができるが、第2図に示す
ように、保持体2にわずかなきずやへこみなどの
欠陥があると、そこへ金属層4を形成するための
めつき液がしみ込み、回路が短絡することがある
という問題が発生した。(Problem to be Solved by the Invention) However, although the wiring board obtained by this conventional manufacturing method for wiring boards in which conductor circuits are embedded can form fine wiring patterns, as shown in FIG. Furthermore, if the holder 2 has a slight flaw or dent, the plating solution for forming the metal layer 4 may seep into the defect, causing a short circuit.
本発明は、微細パターンを容易に得ることので
きる配線板の製造法を提供するものである。 The present invention provides a method for manufacturing a wiring board that allows a fine pattern to be easily obtained.
(課題を解決するための手段)
本発明の配線板の製造法は、導電性を有する保
持体2の表面に所望の形状にめつきレジスト1を
形成し、該保持体2とともに除去できる第1の金
属層5をめつきにより形成し、該保持体2の除去
条件と異なる金属層と他の金属層とからなる第2
の金属層4をめつきにより形成し、前記めつきレ
ジスト1を除去し、第2の金属層4の面に絶縁基
材を重ね合わせ圧着し、前記第2の金属層4が露
出するまで前記第1の金属層5と前記保持体2と
をともに除去することを特徴とする。(Means for Solving the Problems) The method for manufacturing a wiring board of the present invention involves forming a plating resist 1 in a desired shape on the surface of a conductive holder 2, and forming a first plating resist 1 that can be removed together with the holder 2. A second metal layer 5 is formed by plating, and a second metal layer consisting of a metal layer different from the removal conditions of the holder 2 and another metal layer is formed by plating.
A metal layer 4 is formed by plating, the plating resist 1 is removed, an insulating base material is overlaid and pressure-bonded on the surface of the second metal layer 4, and the process is continued until the second metal layer 4 is exposed. The method is characterized in that both the first metal layer 5 and the holder 2 are removed.
すなわち、第1図に示すように、保持体2のわ
ずかなきずやへこみ3の部分を、保持体2ととも
に徐去できる金属で埋めて、その上に回路を保護
する金属層と導体となる金属層を形成し、絶縁基
材中にその回路となる金属を埋めた後、保持体2
と保持体2のわずかなきずやへこみ3の部分を埋
めた金属とをともに除去するものである。 That is, as shown in FIG. 1, small scratches and dents 3 in the holder 2 are filled with metal that can be removed together with the holder 2, and a metal layer that protects the circuit and a metal that becomes a conductor are placed on top of the metal that can be removed together with the holder 2. After forming the layer and burying the metal that will become the circuit in the insulating base material, the holder 2
This removes both the metal that has filled in the small scratches and dents 3 in the holder 2.
本発明に用いる保持体2はステンレス板等に剥
離可能なようにめつきした銅箔でもよく、また、
すでに引き剥がされた銅箔、あるいは圧延された
銅箔を用いることもできる。また、該保持体2と
ともに除去できる第1の金属層5は、保持体2と
同質の金属が好ましく、厚さとしては、前述のと
おり、保持体2のわずかなきずやへこみを埋める
ことができればよく、約3μm位である。 The holder 2 used in the present invention may be a copper foil plated on a stainless steel plate or the like in a peelable manner, and
It is also possible to use copper foil that has already been peeled off or rolled copper foil. The first metal layer 5, which can be removed together with the holder 2, is preferably made of the same metal as the holder 2, and has a thickness that can fill slight scratches and dents in the holder 2, as described above. It is usually about 3 μm.
該保持体2の除去条件と異なる金属層と他の金
属層とからなる第2の金属層4としては、金、ニ
ツケル、はんだ、あるいは、金と銅、ニツケルと
銅等で、単独の場合はそれ自身、2種以上の場合
は第1の金属5に面している金属の除去条件が、
第1の金属5と異なる必要がある。 The second metal layer 4 consisting of a metal layer and another metal layer different from the removal conditions of the holder 2 may be gold, nickel, solder, gold and copper, nickel and copper, etc. itself, in the case of two or more types, the removal conditions for the metal facing the first metal 5 are as follows:
It needs to be different from the first metal 5.
実施例
ステンレス表面を研磨後、全面に30μm厚の硫
酸銅めつきを行つた。次に銅表面をサンドペーパ
ーで研磨後、フオトレジストをロールラミネータ
によりラミネートした。ポジマスクを当て紫外線
を照射した後、現像液をスプレーし現像した。次
に銅めつきを3μmの厚さで行い、研磨でついた
きずを埋め、金めつきを1μmの厚さで行い、さ
らに硫酸銅めつきを30μm行い回路パターンを形
成した。レジスト剥離液に浸漬し、レジストを剥
離した後、黒色酸化処理を行つた後、パターンの
形成された銅箔をステンレス板よりはがし取つ
た。この銅箔を、あらかじめエツチング法で作成
した内層板と接着用プリプレグと位置決めピンに
より位置決めできる金型にセツトし、170℃2時
間・60Kg/cm2の圧力で加熱加圧した。続いて、内
蔵された金めつきが露出するまで表面の銅をエツ
チングして、所望の配線板を製作した。この印刷
配線板は、線幅、線間隔40μmの回路パターンを
有するものである。Example After polishing the stainless steel surface, the entire surface was plated with copper sulfate to a thickness of 30 μm. Next, after polishing the copper surface with sandpaper, a photoresist was laminated with a roll laminator. After applying a positive mask and irradiating it with ultraviolet rays, a developer was sprayed and developed. Next, copper plating was performed to a thickness of 3 μm to fill in the scratches caused by polishing, gold plating was performed to a thickness of 1 μm, and copper sulfate plating was further performed to a thickness of 30 μm to form a circuit pattern. After the resist was removed by immersion in a resist removing solution and a black oxidation treatment was performed, the patterned copper foil was peeled off from the stainless steel plate. This copper foil was set in a mold that could be positioned using an inner layer plate prepared in advance by an etching method, an adhesive prepreg, and positioning pins, and heated and pressed at 170°C for 2 hours at a pressure of 60 kg/cm 2 . Next, the copper on the surface was etched until the built-in gold plating was exposed, producing the desired wiring board. This printed wiring board has a circuit pattern with a line width and line spacing of 40 μm.
(発明の効果)
以上説明したように、本発明により次の効果が
達成された。(Effects of the Invention) As explained above, the following effects have been achieved by the present invention.
(1) 従来工程で発生したシヨートが激減し、歩留
りが向上する。(1) Shoots generated in conventional processes are drastically reduced and yields are improved.
(2) 従来はパターン表面に研磨きずが転写されて
いたが、銅めつきによりきずを埋めることで、
より平滑できずが無いパターン面が得られる。(2) Conventionally, polishing scratches were transferred to the pattern surface, but by filling the scratches with copper plating,
A smoother pattern surface with no defects can be obtained.
第1図は本発明の方法を説明するための断面
図、第2図は従来の方法を説明するための断面図
である。
符号の説明、1……レジストパターン、2……
保持体、3……粗化処理によるきずや空〓、4…
…第2の金属層、5……第1の金属層。
FIG. 1 is a sectional view for explaining the method of the present invention, and FIG. 2 is a sectional view for explaining the conventional method. Explanation of symbols, 1...Resist pattern, 2...
Holder, 3... Scratches and voids due to roughening treatment, 4...
...Second metal layer, 5...First metal layer.
Claims (1)
にめつきレジスト1を形成し、該保持体2ととも
に除去できる第1の金属層5をめつきにより形成
し、該保持体2の除去条件と異なる金属層と他の
金属層とからなる第2の金属層4をめつきにより
形成し、前記めつきレジスト1を除去し、第2の
金属層4の面に絶縁基材を重ね合わせ圧着し、前
記第2の金属層4が露出するまで前記第1の金属
層5と前記保持体2とをともに除去することを特
徴とする配線板の製造法。1 Form a plating resist 1 in a desired shape on the surface of a conductive holder 2, form a first metal layer 5 that can be removed together with the holder 2 by plating, and set the removal conditions for the holder 2. A second metal layer 4 consisting of a metal layer different from the above and another metal layer is formed by plating, the plating resist 1 is removed, and an insulating base material is overlaid and crimped on the surface of the second metal layer 4. A method for manufacturing a wiring board, characterized in that both the first metal layer 5 and the holder 2 are removed until the second metal layer 4 is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12020484A JPS60263495A (en) | 1984-06-12 | 1984-06-12 | Method of producing circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12020484A JPS60263495A (en) | 1984-06-12 | 1984-06-12 | Method of producing circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60263495A JPS60263495A (en) | 1985-12-26 |
| JPH0158878B2 true JPH0158878B2 (en) | 1989-12-13 |
Family
ID=14780479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12020484A Granted JPS60263495A (en) | 1984-06-12 | 1984-06-12 | Method of producing circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60263495A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2984595A (en) * | 1956-06-21 | 1961-05-16 | Sel Rex Precious Metals Inc | Printed circuit manufacture |
| JPS5250570A (en) * | 1975-10-20 | 1977-04-22 | Seiko Instr & Electronics | Method of producing circuit substrate |
| JPS5296360A (en) * | 1976-02-09 | 1977-08-12 | Yamamoto Mfg | Embedded printed circuit substrate and method of producing same |
| JPS5381966A (en) * | 1976-12-27 | 1978-07-19 | Hirotoshi Nomura | Method of producing electric circuit part |
-
1984
- 1984-06-12 JP JP12020484A patent/JPS60263495A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60263495A (en) | 1985-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59215795A (en) | Method of producing printed circuit | |
| EP0483979A1 (en) | Method for producing printed circuit boards | |
| US7169313B2 (en) | Plating method for circuitized substrates | |
| JPH04100294A (en) | Manufacture of printed wiring board | |
| KR100343389B1 (en) | Method of manufacturing multilayer wiring boards | |
| JP3402372B2 (en) | Manufacturing method of wiring board | |
| JPH035078B2 (en) | ||
| JPS6337515B2 (en) | ||
| JPWO2000030420A1 (en) | Method for manufacturing a multilayer wiring board | |
| JPH0158878B2 (en) | ||
| JPS6182497A (en) | Manufacture of printed circuit board | |
| JPH01290289A (en) | Conductor pattern formation method | |
| JP3599957B2 (en) | Method for manufacturing multilayer wiring board | |
| EP0239197B1 (en) | Process for producing a metallic pattern | |
| JPH01295487A (en) | Manufacture of printed wiring board with thick plate conductor | |
| JPH1117315A (en) | Manufacture of flexible circuit board | |
| RU2854162C1 (en) | Method of combined positive manufacturing of printed circuit boards with a conductor pattern thickness of the outer layers of more than 150 mc | |
| JP4252227B2 (en) | Manufacturing method of double-sided flexible circuit board | |
| JPS55111142A (en) | Manufacturing method of lead wire for semiconductor device | |
| JPH06252529A (en) | Manufacture of printed wiring board | |
| JPH04268783A (en) | Composite circuit board | |
| JPS63283098A (en) | Formation of pattern | |
| JPS62277789A (en) | Manufacture of wiring board | |
| JPS6356991A (en) | Manufacture of printed wiring board | |
| JPS5916930B2 (en) | Method of manufacturing laminates |