JPS55111142A - Manufacturing method of lead wire for semiconductor device - Google Patents

Manufacturing method of lead wire for semiconductor device

Info

Publication number
JPS55111142A
JPS55111142A JP1882679A JP1882679A JPS55111142A JP S55111142 A JPS55111142 A JP S55111142A JP 1882679 A JP1882679 A JP 1882679A JP 1882679 A JP1882679 A JP 1882679A JP S55111142 A JPS55111142 A JP S55111142A
Authority
JP
Japan
Prior art keywords
layer
specially treated
lead wire
layers
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1882679A
Other languages
Japanese (ja)
Inventor
Manabu Bonshihara
Hiroshi Yokota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1882679A priority Critical patent/JPS55111142A/en
Publication of JPS55111142A publication Critical patent/JPS55111142A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To make reliability of etching and plating processes for lead wire formation higher by a method wherein after the tape is attached to metal foil which has the layers on both surfaces that are treated by electroplating, the inner lead is formed by gold plating followed by removal of electroplated layer of the foil.
CONSTITUTION: The copper alloy foil 1 which has the specially treated layers 4, 4' of both surfaces which are formed by eletroplating such as copper pyrophosphate process etc. is attached to the polyester tape 10 by means of adhesive agent 11 and the pattern of inner lead is formed by photo etching. Continuously the specially treated layers are removed in the bath of ferric chloride solution and unpeeled part 9 of photoresist is taken off with the exception of the part of the specially treated layer 4 covered with adhesive agent layer 11. After this process the lead is completed by apllying gold plate layer 12. Thus because the unremoved parts of photoresist film which is left unremoved at the lead wire pattern etching process and etc. are also removed at the same time by removing the specially treated surface layer that is electroplated and the defectless and highly reliable gold plated layer 12 is achievable.
COPYRIGHT: (C)1980,JPO&Japio
JP1882679A 1979-02-20 1979-02-20 Manufacturing method of lead wire for semiconductor device Pending JPS55111142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1882679A JPS55111142A (en) 1979-02-20 1979-02-20 Manufacturing method of lead wire for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1882679A JPS55111142A (en) 1979-02-20 1979-02-20 Manufacturing method of lead wire for semiconductor device

Publications (1)

Publication Number Publication Date
JPS55111142A true JPS55111142A (en) 1980-08-27

Family

ID=11982358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1882679A Pending JPS55111142A (en) 1979-02-20 1979-02-20 Manufacturing method of lead wire for semiconductor device

Country Status (1)

Country Link
JP (1) JPS55111142A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365633A (en) * 1986-09-05 1988-03-24 Hitachi Cable Ltd Film carrier for semiconductor device
JPS63296346A (en) * 1987-05-28 1988-12-02 Hitachi Cable Ltd Film carrier for semiconductor device
US4975739A (en) * 1988-10-21 1990-12-04 Nippondenso Co., Ltd. Electromagnetic relay

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365633A (en) * 1986-09-05 1988-03-24 Hitachi Cable Ltd Film carrier for semiconductor device
JPS63296346A (en) * 1987-05-28 1988-12-02 Hitachi Cable Ltd Film carrier for semiconductor device
US4975739A (en) * 1988-10-21 1990-12-04 Nippondenso Co., Ltd. Electromagnetic relay

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