JPH0159662B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION It is an object of the present invention to propose a VTR phase adjustment device that can perform phase adjustment reliably and quickly.

Conventionally, when performing a phase adjustment operation to adjust the running status of a VTR to a reference time code signal obtained from an external source, the reference time signal and the playback time code obtained by reproducing the time code signal recorded on the tape of the VTR are used. The vehicle was compared with the signal, and the VTR's running was adjusted based on the comparison results. that time,
If the playback time code signal is behind the target reference time signal, the tape running speed is set slightly faster than 1x speed, and if it is running in the opposite direction, the tape running speed is set slightly slower than 1x speed to match the time signal. When the time code signals matched, the VTR was locked into playback mode. However, even if the VTR is put into playback mode at the timing when the reference time signal and playback timecode signal match, it may accidentally lock onto the adjacent frame depending on how far the frame phases of the two differ. . Once the VTR locks onto the adjacent frame, it takes a considerable amount of time to redo the phase adjustment.

Therefore, the present invention aims to propose a VTR phase adjustment device that makes it possible to always lock the VTR in the correct phase adjustment state when adjusting the phase of the VTR to a reference time signal.

An embodiment of the present invention will now be described in detail with reference to FIG. 1 is a VTR. The magnetic tape TP used in this VTR 1 has a slant track T in which a video signal is stored for each field as shown in Fig. 2, and a slant track T in which a video signal is stored for each field (=2 fields) is formed on the side edge. Control signal
CTL is recorded. V is slant track T
This is the vertical synchronization signal in the video signal (field signal) recorded in the field. TCD is the video signal (field signal) recorded on the slant track T.
This is a time code signal corresponding to the middle frame, and is located near the vertical synchronization signal V. The time code signal TCD in this case is called the VITC method, and the time code signal recorded on the side edge of the tape (SMPTE
method). Note that in the case of the SMPTE system, the sync bit signal of the time code signal can be used as a control signal.

This VTR 1 is equipped with a tape guide drum (consisting of a rotating upper drum and a fixed lower drum) having a pair (or one) of rotating magnetic heads, and the tape TP is wound on this tape guide drum in a predetermined manner. It is made to guide and run so as to be wrapped at a given angle.

Further, this VTR 1 is provided with a tape running drive means, which consists of a capstan, a capstan motor (DC motor), its motor control circuit, etc., and it is possible to supply a control signal to this motor control circuit from the outside (remote control). The tape speed can also be varied using the tape control.

Further, the above-mentioned time code signal is reproduced by a rotating magnetic head, and the control signal CTL is reproduced by a fixed magnetic head.

2 is a phase adjuster for VTR1, and between these,
They are connected to each other through various cables L.
This phase adjuster 2 will be explained below. 4 is a central processing unit (microcomputer), which controls each circuit described later. Note that 4a is a bus.
5 is a control signal reproducing circuit for reproducing the framed control signal CTL from the VTR 1; 6
is a time code signal reading circuit that reads the reproduced time code signal from the VTR1. 7 is VTR1
In addition to controlling the tape running drive means of the VTR
This is a control circuit that supplies a reproduction command signal to 1. 8
is a reference clock that generates a reference clock signal based on a reference frame pulse, which will be described later. Reference numeral 9 denotes a reference frame pulse generation circuit that generates a reference frame pulse based on the output of the external reference synchronization signal generation circuit 3. The reference frame pulse from the reference frame pulse generation circuit 9 is supplied to circuits 5, 6, 7 and 8. Incidentally, various synchronization signals from the external reference synchronization signal generation circuit 3 are also supplied to the VTR 1.

The control circuit 7 receives a reproduction control signal from the control signal reproduction circuit 5, a tape current time signal and its tape target time signal from the time code reading circuit 6, and a reference current time signal and its reference target time signal from the reference clock 8. , reference frame pulses from a reference frame pulse generation circuit 9 are supplied, respectively.

Next, a specific circuit of a part of the control circuit 7 will be explained with reference to FIG. 11 is approximately 30Hz playback control signal
The input terminal of CTL (FIG. 4A), 12 is the input terminal of clock pulse CP ₀ , and 13 is the input terminal of 30 Hz reference frame pulse SFP (FIG. 4C). _F1 ～
_F4 is a D-type flip-flop circuit, and a clock pulse _CP0 of, for example, 39.4 KHz from the input terminal 12 is supplied to each of its T input terminals.

16 is an 8-bit counter, and 18 is an 8-bit latch circuit that latches the contents of the counter. A reproduction control signal CTL is supplied to the D input terminal of the flip-flop circuit _F1 , and its non-inverted output is supplied to the D input terminal of the flip-flop circuit _F2 . The inverted output of the flip-flop circuit _F1 and the non-inverted output of the flip-flop circuit _F2 are supplied to a NAND circuit 14, whose output is used as a clear pulse.
It is supplied to the counter 16 as CLP (FIG. 4A). Note that this clear pulse CLP is a signal in which the falling edge of the reproduction control signal CTL is synchronized with the clock pulse _CP0 . Further, the clock pulse CP ₀ is supplied to the frequency divider 17 and divided by, for example, 1/n (=1/16) to obtain the clock pulse CP ₁ (FIG. 4B) with a frequency of 2.46 kHz, which is sent to the counter 16. and count it.

Further, the reference frame pulse SFP is supplied to the D input terminal of the flip-flop circuit _F3 , and its non-inverted output is supplied to the D input terminal of the flip-flop circuit _F4 . The inverted output of the flip-flop circuit _F3 , the flip-flop circuit _F4 , and the non-inverted output are supplied to the NAND circuit 15, and the output is sent to the latch circuit 18 as a preset pulse PSP (FIG. 4C).
is supplied to Note that the preset pulse PSP is a clock pulse that corresponds to the falling edge of the reference frame pulse SFP.
This is a signal synchronized to CP ₀ .

Thus, in the latch circuit 18, the playback control signal
The number of pulses F _P (=D ₁ ,
D ₂ , D ₃ , . . . ) (FIG. 4D) are obtained, and these are latched during the period of the reference frame pulse SFP as shown in FIG. supplied to the port. In addition, the clock pulse
Divide CP ₀ by 1/n to obtain clock pulse CP ₁ ,
The reason why this is supplied to the counter 16 is to prevent the counter 16 from becoming saturated even when the tape speed is approximately 1/3 times the tape speed, and to enable the detection of the phase difference with the reference frame pulse.

Also, clock pulse CP1 is clear pulse CLP.
The second counter 19, which is cleared by the second counter 19, counts, and the contents of the count are supplied to the latch circuit at the timing of the clear pulse CLP. As a result, a tape speed detection signal is obtained and supplied to the I/O port of the central processing unit 4.

Next, the phase tone procedure and process will be explained with reference to the curve diagram in FIG. 5 and the flowchart in FIG. 6.
The horizontal axis of FIGS. 5A and 5B is time, the vertical axis of FIG. 5A is tape speed, and the vertical axis of FIG. 5B is time. In FIG. 5B, CCT indicates the reference current time based on the clock signal of the reference clock 8, TCT indicates the target time, CTT indicates the tape current time based on the reproduction time code signal TCD, and TTT indicates the target time.

First, the tape TP of the VTR 1 is temporarily run, the time code signal TCD is reproduced, and the reading circuit 6 detects the tape start time. Further, the tape target time TTT is set in the reading circuit 6.
Also, tape start time, tape target time TTT
The reference start time and reference target time TCT of the reference clock 8 are set in consideration of the total processing time and the total processing time. Then, at the same time as starting the clock time of the reference clock 8, the tape TP is fast-forwarded or rewound, and for example, 3 frames (=6 fields) of the tape target time TTT are started.
At the previous or subsequent time _t1 , the speed of the tape is reduced to around one time the low speed (1x speed), and thereafter the running drive of the tape is controlled as shown in FIGS. 5 and 6.

A phase difference pulse F _P and a latch circuit 20 based on the phase difference between the reproduction control signal CTL and the reference frame pulse SFP obtained from the latch circuit 18 in FIG.
It is determined whether the tape speed is 1x speed or not based on the tape speed detection signal obtained from 1. If the tape speed is not 1x speed, it is determined again after one frame whether the tape speed is 1x speed or not. When the tape speed is 1x, the tape
The phase of the playback control signal CTL from the TP and the reference frame pulse SFP is compared, and the tape target time is
Tape difference time between TTT and tape current time CTT
Reference difference time TCT between reference target time TCT and reference current time CCT based on TTT-CTT and reference clock signal
−CTT and the phase difference (number of phase difference pulses) F _P is within a predetermined value, e.g. 60<F _P
<100 and the time difference d disappears, that is, the travel drive means is controlled so that d=(TTT-CTT)-(TCT-CCT)=0. In this case, TTT-CTT=TCT-CCT=0 may of course be used.

In other words, the phase difference (number of phase difference pulses) F _P is 60<F _P
<100 is determined at a position within ±90°, which is the possible phase difference of capstan lock, with respect to the track of the frame at the tape target time TTT, and when the time code signal TCD is being played back. A reproduction command signal is generated at a possible position so that reproduction can be started accurately from the frame of the tape target time TTT.

Also, in cases where 60<F _P <100, 60>F _P
When , the tape TP is driven at 1.08x speed and F _P > 60
The tape position is corrected so that 60>F _P does not hold, that is, when F _P >100, the tape TP is driven at 0.92 times the speed and the tape position is corrected so that F _P <100.

Then, if 60<F _P <100, d=(TTT−
CTT) - (TCT - CCT) is determined to be d=0, and if d<0, the tape is driven at 0.88x speed and the tape position is corrected so that d>0, and d< When it is not 0, that is, when d>0, the tape is driven at 1.17 times the speed, the tape position is corrected so that d<0, and the tape speed is detected again.

Then, when d=0 at time _t2 ,
A playback command signal is given to the VTR from the control circuit 7, and shortly thereafter, at time _t3 , the tape target time is reached.
Start playback from the TTT frame track.
Note that there is also a case where t ₂ = t ₃ .

In this way, the running state of the VTR is controlled so that the reproduced time code signal obtained from the VTR matches the reference time signal obtained from the reference signal,
In addition, when the phase difference between the reference frame pulse and the reproduction frame pulse is within ±90°, the reproduction command signal is given to the VTR.
The VTR completes the pull-in operation to the correct frame phase state without being erroneously locked to an adjacent frame and is locked, completing the phase adjustment.

Instead of the clock signal of the reference clock 8 mentioned above, another
A clock signal based on a time code signal played from a VTR tape may be used.

The phase adjustment device according to the present invention is suitable for controlling the playback (broadcast) start position (time) of a videotape or for electronic editing of a videotape.

According to the present invention described above, it is possible to obtain a VTR phase adjustment device that can perform phase adjustment reliably and quickly.

The time code signal recorded on tape is
Either the VITC method (when the time code signal is recorded on the slant track), the SMPTE method (when the time code signal is recorded on the side edge of the tape), or a combination of both methods may be used.
This is particularly suitable for the VITC method.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a tape pattern, FIG. 3 is a block diagram showing a part of the circuit in FIG. 1, and FIG. 4 is a waveform diagram. , FIG. 5 is a characteristic curve diagram, and FIG. 6 is a flowchart. TP is a tape, and 7 is a control circuit.

Claims (1)

[Claims] 1 Using a tape on which a video signal, a control signal for each frame of the video signal, and a time code signal corresponding to the frame of the video signal are recorded,
A control circuit is provided for controlling a traveling drive means for driving the tape in the VTR, and compares the phase of the reproduction control signal from the tape with the reference frame pulse, and also compares the phase of the reproduction control signal from the tape with the reference frame pulse, and also controls the tape at the target tape time and the tape current time. The time difference is compared with the reference time difference between the reference target time and the reference current time based on the reference clock signal, and the traveling is performed so that the phase difference resulting from the phase comparison is within a predetermined value and the time difference resulting from the time comparison is eliminated. A VTR phase adjustment device characterized by controlling a driving means.