JPH0160967B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a negative capacitance circuit that can be used to cancel stray capacitance in a circuit and eliminate the adverse effects of the capacitance.

Electrical or electronic circuits inevitably have stray capacitance, such as interline or ground capacitance of cables or parasitic capacitance of components, which can have various adverse effects. For example, if a stray capacitance Cs is attached to an arbitrary part P of the circuit as shown in Figure 1, and the power supply side of that part is represented by a series impedance Z ₁ with the voltage source VS as shown in Figure a, then the part P When the voltage of
Moreover, the degree depends on the frequency. Assuming that the voltage source is the antenna and the point P is the input terminal of the receiver, a voltage drop at the point P causes a deterioration of the S/N ratio, which is undesirable. It is also possible to connect an inductance in parallel with the stray capacitance Cs to compensate for the attenuation, but in this case there is a problem that it is not effective unless the parallel resonance frequency of the capacitance Cs and inductance L is around. If negative capacitance can be realized, it will have the same frequency characteristics, so connect the negative capacitance in series or parallel with the stray capacitance to cancel out the stray capacitance over a wide frequency range and eliminate its negative effects. Can be done.

As is well known, the impedance of a capacitor with capacitance Cs is -j1/ωC, so the impedance Ze of negative capacitance -C is Ze=j1/ωC or -1/jωC, and the phase relationship is the same as that of inductance, and the absolute value is It is the opposite of inductance and the same as a capacitor, and decreases as the frequency increases. When such negative capacitance -C is placed in parallel with stray capacitance Cs as shown in Figure 1 c or in series as shown in Figure 1 d, the combined impedance is Ze ₁ expressed by the following formula at Figure 1 c, In the case of d in the figure, Ze ₂ is also expressed by the following formula.

Ze ₁ = 1/jω(Cs-c) ……(1) Ze ₂ = 1/jω・C-Cs/CsC ……(2) When Cs=C, equation (1), that is, in case of parallel connection
Ze ₁ = ∞, and equation (2), that is, when connected in series
Ze ₂ = 0, which is the same as there being no stray capacitance.

A conventional negative capacitance circuit that realizes such negative capacitance is shown in FIG. In this figure, Tr ₁ and Tr ₂ are npn transistors, Ce is a capacitor, and these are connected as shown. To explain the operation of this circuit,
Transistor Tr ₁ is an emitter follower and Tr ₂
is a grounded base, and approximately the output impedance of the emitter follower is zero and the input impedance is infinite, and the input impedance of the grounded base is zero and the output impedance is infinite, so the following can be said. When a voltage E is applied to the input terminal a, that is, the base of transistor Tr ₁ , the transistor
If we ignore the base-emitter voltage of Tr ₁ and Tr ₂ (this is represented by the emitter resistance in AC terms, but we will do an analysis that takes emitter resistance into consideration later), a voltage of E is applied to the capacitor Ce, and jωCeE A current I equal to flows. This current is the transistor
Input terminal a through the emitter and collector of Tr ₂
The transistor seen from terminal a
The impedance of the circuit of Tr ₁ and Tr ₂ is negative,
Since I=-jωCeE, the impedance Ze ₃ is Ze ₃ =E/I=-1/jωCe (3), and thus a negative capacitance with a capacitance value of -Ce is obtained.

Although FIG. 2 shows only the exchange circuit section, examples of DC bias circuits for this are shown in FIGS. 3a, b, and c. In these figures, R ₁ to R ₁₁ and R _E are resistances, L is inductance, Cp ₁ to _{Cp 3} are bypass capacitors,
_D1 to _D3 are a group of diodes. Transistor Tr ₁
A bias circuit is required at the input terminal a in order to apply a bias voltage to the base of the transistor Tr ₂ and to flow a bias current to the transistor Tr 2. However, in the conventional circuit shown in Fig. 2, the collector of the transistor Tr ₂ is connected to the input terminal a. Since this bias circuit is connected in parallel to input terminal a, its AC impedance is large enough to create a circuit with good characteristics.
Impedance needs to be small in terms of DC bias. For this reason, the following considerations are being made. That is, in FIG. 3a, a bias circuit is constructed by inserting an inductance L in series with a resistor _R1 between the power supply Vcc and the input terminal a, and the alternating current resistance is sufficiently increased. In addition, in FIG. 3b, a transistor Tr ₃ is used for the bias circuit, and a resistor R ₆ , connected to the power supply Vcc,
Transistors Tr ₁ and Tr ₂ are biased by a series circuit of R ₇ , but transistor Tr ₃ is made an emitter follower and its emitter resistor R ₅ and the above-mentioned resistors R ₆ and R _{7 are} biased.
A capacitor Cp ₂ is connected to the connection point Q of the resistor R ₆ to reduce the alternating current flowing through the resistor R 6 , that is, to increase the alternating current resistance of the resistor R ₆ . Furthermore, in the circuit of FIG. 3c, the bias circuit includes a transistor Tr ₅ , a resistor R ₁₀ ,
A constant current circuit consisting of _R11 and a diode group _D2 formed by connecting multiple diodes in series is used to increase the impedance, and a transistor
A constant current circuit consisting of Tr ₄ , resistors R ₆ and R ₉ , and diode group D ₃ determines the current of transistor Tr ₁ and determines its base voltage.

In this way, in the conventional negative capacitance circuit shown in Fig. 2, the collector of transistor Tr ₂ is directly connected to the input terminal, so the bias circuit at input terminal a is small in terms of DC bias, and the AC impedance is small. needs to be sufficiently large, and it is necessary to configure a bias circuit using the inductance L, or the transistor Tr ₃ and the bypass capacitor Cp ₂ , or the transistor Tr ₅ and the diode group D ₂ .

Therefore, there are disadvantages in that the configuration of the bias circuit becomes complicated and the circuit becomes larger.

Therefore, it is an object of the present invention to realize a negative capacitance circuit which has a simple structure and can extremely easily configure a bias circuit provided at the input terminal.
The negative capacitance circuit of the present invention includes a control circuit including a capacitor, and a transistor that receives an input voltage, applies the input voltage or a voltage proportional to the input voltage to the capacitor, and returns a current determined by the reactance of the capacitor to the input terminal. The control circuit has a first transistor and a second transistor, the first transistor receives an input voltage at its base, its collector connects to the base of the second transistor, and its emitter connects to the base of the second transistor. The emitter of the second transistor is connected to the series connection point of the first and second resistors, the emitter of the second transistor is connected to the first resistor and one end of the capacitor, and the other end of the capacitor is connected to the first resistor. connected to the base and the second
This is characterized in that the other end of the resistor is grounded, which will now be described in detail with reference to embodiments.

FIG. 4 is a circuit diagram showing one embodiment of the present invention. In the same figure, Tr ₆ is an npn transistor that is the first transistor, Tr ₇ is a pnp transistor that is the second transistor, Ce is a capacitor,
R ₁₃ and R ₁₄ are the first and second resistors, respectively, and these are connected as shown in the figure.This circuit is a voltage feedback type, whereas the conventional circuit shown in Figure 2 is of a current feedback type. It is a type. This circuit has high input impedance and low output impedance. Moreover, this circuit consists of two transistors Tr ₆ ,
A common-mode amplifier is configured using Tr ₇ and feedback amplification, and negative capacitance is obtained by connecting a capacitor Ce in parallel between the input and output terminals.

In this circuit, if the amplification factor of transistor Tr ₇ is β, then the following formula holds true.

E=1/jωCe (E/R ₁₄ −i−iβ)+R ₁₃
/R ₁₄ E−iR ₁₃ +E……(4) I=E/R ₁₄ −i−iβ……(5) Here, by appropriately selecting the values of resistors R ₁₃ , R ₁₄ and capacitor Ce, Since β≫1, Ze=E/I≒−R ₁₄ /jωCeR ₁₃ (6), and a negative capacitance of −R ₁₃ Ce/R ₁₄ is created.

FIG. 5 shows a specific example in which a DC bias circuit is added to the AC circuit shown in FIG. In this circuit R ₁₅ ~ _{R 18}
is a resistor and Cp ₄ is a capacitor. In this circuit, resistor R ₁₄ in FIG. 4 is equal to the parallel resistance of resistors R ₁₄ , R ₁₅ , and R ₁₆ .

In the negative capacitance circuit shown in Fig. 4, the collector of the second transistor _Tr7 , which is the output terminal, is connected to the capacitor Ce.
Since the bias circuit is connected to the input _{terminal a} via Impedance can be increased. For this reason,
As can be seen from FIG. 5, in the negative capacitance circuit of the present invention, the DC bias circuit can be more easily constructed with fewer elements than the conventional circuit shown in FIG. Furthermore, since the negative capacitance circuit of the present invention is a common-mode amplifier with gain, it is particularly effective when used as a circuit that requires amplification.

As explained in detail above, according to the negative capacitance circuit of the present invention, since the capacitor is connected between the base of the first transistor, which is the input end, and the collector of the second transistor, which is the output end, the bias The circuit can be configured extremely easily.

[Brief explanation of drawings]

Figures 1 a to d are circuit diagrams explaining a floating circuit and its elimination method, Figure 2 is a circuit diagram showing a conventional example, Figures 3 a, b, and c are circuit diagrams showing specific examples of the conventional circuit; Figure 4 is a circuit diagram showing an embodiment of the present invention, and Figure 5 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing a specific example of the present invention. In the drawing, VS is a voltage source, CS is a current source, Cs is a stray capacitance, -C is a negative capacitance, Tr ₁ to _{Tr 7} are transistors,
R ₁ to R ₁₈ and R _E are resistances, L is inductance,
Cp ₁ to _{Cp 4} are bypass capacitors, Ce is a capacitor, and D ₁ to _{D 3} are diode groups.

Claims (1)

[Claims] 1 a capacitor, receiving an input voltage and applying the input voltage or a voltage proportional to it to the capacitor;
A negative capacitance circuit comprising a control circuit including a transistor that returns a current determined by the reactance of the capacitor to an input terminal, the control circuit having a first transistor and a second transistor, the first transistor having a base receives the input voltage, and the collector
The emitter of the transistor is connected to the series connection point of the first and second resistors, the emitter of the second transistor is grounded, and the collector is connected to the first resistor and one end of the capacitor. A negative capacitance circuit characterized in that the other end of the second resistor is connected to the base of the first transistor, and the other end of the second resistor is grounded.