JPH0161009B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital protection relay that is applied to a power system and has an improved analog input circuit for detecting accidents.

A conventional example of this type of circuit is an analog input circuit for a digital protective relay shown in FIG. In the figure, 1a to 1h are filters for removing noise wave components unnecessary for relay determination, 2a to 2h are sample/hold circuits for simultaneous sampling provided corresponding to the respective filters 1a to 1h,
3 is an AD conversion circuit, and 4 is a multiplexer for selecting an input to the AD conversion circuit. Furthermore, a to h represent analog input signals, and p represents a digital output signal. These analog input signals a to h
is introduced after performing level conversion, current/voltage conversion, waveform shaping, etc. on various status signals of each system such as detection transformer PT and detection current transformer CT arranged in the power system.

Next, the operation will be explained. The voltage or current waveform introduced from the grid contains DC components and harmonic components, and in order to prevent these from falsifying the results of accident determination, filters 1a to 1h are used to extract only the necessary components and the corresponding sample and hold components are used. All channels are held simultaneously by circuits 2a to 2h,
The previous voltage level is maintained at the output of each sample-and-hold circuit 2a to 2h for a certain period of time. The multiplexer 4 sequentially scans each of these channels and connects them to the AD conversion circuit 3. The series of operations is carried out by the sample and hold circuit 2a.
The process starts from a hold state of 2h to 2h, and each channel is connected to the AD converter 3 according to sequential time-division scanning, and ends when all channels are time-divisionally converted into digital signals.

Since the conventional circuit is constructed as described above, as the number of multi-channel inputs increases, the number of filters and sample-and-hold circuits will need to correspond to the corresponding number of channels, which obviously results in an increase in the number of components. In addition, each filter and sample/hold circuit often needs to be equipped with offset adjustment and gain adjustment circuits depending on the magnitude of the input analog signal for characteristic management purposes. There were drawbacks such as the need to provide duplicates.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by realizing the function of an operational amplifier for a filter using an operational amplifier in the sample-and-hold circuit, the number of parts can be reduced and the number of duplications can be reduced. The purpose of the present invention is to provide a digital protective relay with an analog input circuit that achieves low cost, space savings, and improved reliability by eliminating the adjustment function that previously existed.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of an input circuit applied to a digital protective relay according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, so a description thereof will be omitted. In Fig. 2, 5 is a filter/sample and hold circuit (hereinafter abbreviated as FSH circuit) that integrates a filter circuit and a sample and hold circuit, 4 is a multiplexer, and 3
is an AD conversion circuit. The FSH circuit 5 has low-pass type, high-pass type, and band-pass type.
Specific configuration examples of the circuits are shown in FIGS. 3, 4, and 5, respectively, and further, a specific configuration example of the filter circuit provided in the FSH circuit 5 is shown in FIG.

Before explaining the operation of the present invention, the sample and hold circuit 10 will be explained based on FIG. In the same figure, 15 and 16 are operational amplifiers, 17 is a switch,
18 is a hold capacitor, 19 is an input terminal, 2
0 is an output terminal, and 21 is a control signal input terminal (hereinafter abbreviated as S/H terminal) for controlling opening and closing of the switch.

Now, when a control signal is applied to this S/H terminal, the switch 17 is closed, so the sample and hold circuit 10 as a whole becomes a series connection of two stages of voltage followers, and is externally connected as a non-inverting operational amplifier. As shown, the hold capacitor 18 has the same potential as the input terminal 19 and the output terminal 20. On the other hand, when the control signal is released and the switch 17 is opened, the operational amplifier 16
The potential of the hold capacitor 18 is applied to the input of the switch 17, and the potential is held at the value immediately before the switch 17 is opened. Therefore, even if the potential of the input terminal 19 changes, the previous potential of the output terminal 20 is maintained as the potential of the hold capacitor 18. Hereinafter, the state in which the switch 17 is closed will be referred to as sampling mode, and the state in which it is open will be referred to as hold mode.

The common use of the operational amplifier in the sample hold circuit 10 and the operational amplifier of the filter circuit as described above will be explained. FIG. 3 shows a specific configuration example of a low-pass filter 11 to which the sample-hold circuit 10 described in FIG. 6 is applied. 10 is a sample hold circuit, 22 and 23 are filter resistors, 2
4 and 25 are filter capacitors, 18 is a hold capacitor, 27 is an input terminal, and 28 is an output terminal.

In FIG. 3, when the sample and hold circuit 10 is viewed as a non-inverting connected operational amplifier, the relationship between the input terminal 27 and the output terminal 28 can be expressed by the following equation (1).

V ₂ /V ₁ = 1/R ₁ R ₂ C ₁ C ₂ /S ² +S (1/R ₁ C ₁ +1/R ₂ C ₁ ) + 1/
R ₁ R ₂ C ₁ C ₂ ...(1) However, V ₁ is the potential of the input terminal 27, V ₂ is the potential of the output terminal 28, and S is a variable expressed by jω, that is, "2π × frequency" . When changing S, the analog signal voltage V ₂ and
The relationship of V ₁ is that when S=0, V ₂ /V ₁ =1, and S=
When ∞, V ₂ /V ₁ =0. Therefore, the filter 11 functions as a sample-and-hold circuit and realizes a second-order low-pass filter. That is, in the sampling mode, it operates as a second-order low-pass filter. Further, equation (1) is the same equation as an active filter realized using a non-inverting amplifier, and its operation is well known. Further, when the hold mode is entered, the output potential held immediately before the mode switching is performed, as described in the explanation of the sample and hold operation. Since this output signal is an output signal during filter operation in sampling mode, the signal waveform of the analog input signal from which unnecessary components have been removed is held. Since the output impedance of the sample and hold circuit 10 is very small, the influence of potential changes at the input terminal 27 through the capacitor 24 can be ignored.

In the hold mode, the feedback loop by capacitor 24 is opened, so resistors 22 and 23
The potential from which high frequencies are removed by the low-pass primary filter formed by the capacitor 25 is sample hold 1.
0 input terminal, and when switching from this state to sampling mode, it changes to a second-order low-pass filter, but since the follow-up time is extremely short, no problem arises in terms of application.

As described above, the operational amplifier of the sample-and-hold 10 can be used both as an operational amplifier for the active filter in the sampling mode and as an operational amplifier for the original sample-and-hold circuit in the hold mode, and that there is no problem with these two functions. It will be revealed.

FIG. 4 and FIG. 5 both show an FSH applied to a digital protective relay according to another embodiment of the present invention.
As examples of the circuits 12 and 13, FIG. 4 shows a specific circuit diagram of a high-pass filter, and FIG. 5 shows a specific circuit diagram of a band-pass filter. In addition, in these figures, the third
The same reference numerals as in the figures indicate the same or corresponding parts, so
Detailed explanation will be omitted. In the embodiment shown in FIG. 4, a high-pass filter is formed by filter resistors 22, 23 and filter capacitors 24, 25, and in the embodiment shown in FIG.
3, 26, and filter capacitors 24, 25, the bandpass filter functions as an active filter together with the operational amplifier of the sample and hold circuit 10, as in the embodiment of FIG.

As described above, according to the present invention, the filter circuit and the sample/hold circuit are integrated and configured,
Since the operational amplifier of the filter circuit is no longer required, cost and space savings are achieved, as well as improved reliability and lower power consumption.In addition, the sample and hold circuit is connected in series with two stages of voltage followers in sampling mode. As a result, the input circuit has an extremely high input impedance, and since the value of the resistor element that makes up the filter circuit can be set high, the capacitor capacity can be reduced when the resistor capacitor circuit time constant is constant, reducing cost and space. It is advantageous in this respect.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an analog input circuit applied to a conventional digital relay, Fig. 2 is a circuit diagram of an analog input circuit applied to a digital relay according to an embodiment of the present invention, and Fig. 3 is the same. 4 and 5 are circuit diagrams of another FSH circuit applied to a digital relay according to another embodiment of the present invention, and FIG. Shown in Figures 3 to 5.
Each shows a circuit configuration diagram of a sample-and-hold circuit applied to the FSH circuit. 1a to 1h...filter circuit, 2a to 2h...
Sample hold circuit, 3...Analog-digital converter, 4...Multiplexer, 5a to 5h
...FSH circuit, 10...sample hold circuit,
11...Low pass type FSH circuit, 12...High pass type FSH circuit, 13...Band pass type FSH circuit,
15, 16... operational amplifier, 17... switch,
18, 24, 25... Capacitor, 22, 23,
26...Resistance. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a digital protection relay that converts various analog state signals of the power system detected through a detection transformer, detection current transformer, etc. arranged in the power system into a digital state signal after time-division scanning with a multiplexer, a filter circuit that is of a pass type, a high-pass type, or a band-pass type and that introduces the analog state signal; a first operational amplifier that inputs the output signal of the filter circuit; and a first operational amplifier that supplies the output signal to the multiplexer. When a second operational amplifier and a control signal are applied, the first and second operational amplifiers
a filter/sample-and-hold circuit that integrates a switch that connects operational amplifiers in series and a sample-and-hold circuit that has a hold capacitor that holds the input potential of the second operational amplifier when the switch is open; A digital protection relay featuring: