JPH0161187B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit testing device, and more particularly to a circuit for determining the quality of integrated circuits.

One of the inspection items for integrated circuits is an inspection that classifies the speed according to its performance. Conventionally, such grade classification has relied on an inspection method in which a test pattern is run multiple times for each speed standard to determine which grade the integrated circuit's spade capability belongs to. However, as the circuit configuration inside integrated circuits becomes more complex and diverse,
As test patterns have become longer, it has been desired to shorten inspection time in order to reduce inspection costs.

An object of the present invention is to provide an integrated circuit testing apparatus having a novel determination circuit that solves the above-mentioned conventional drawbacks.

A feature of the present invention is that a comparison judgment circuit of an integrated circuit testing device is provided with a plurality of strobe signals and defect detection circuits corresponding to each of them, and compares each strobe signal with expected data at different strobe timings to judge whether the data is good or bad. The present invention relates to an integrated circuit testing apparatus having a comparative judgment method characterized in that results can be recognized independently for each strobe. For example, when comparing and inspecting an operating waveform with an expected waveform, the pass/fail judgment results are recognized in response to each of multiple strobes independently, with the aim of making pass/fail judgments in chronological order within one clock cycle. Equipped with a circuit to obtain
This is related to the comparative judgment method.

According to the present invention, a reduction in the number of tests related to speed inspection can be expected.

Embodiments of the present invention will be described below with reference to the drawings while comparing them with the conventional system.

FIG. 1 is a principle diagram showing one row of comparison/judgment circuits for one channel according to the conventional method, and an example of its operation is shown below.

In the figure, a level comparison circuit 1 compares device output data D with a high level standard C and a low level standard E, and generates a level comparison result signal G. The level comparison result signal is sent to a failure detection circuit 2. Using the detection enable signal A, detecting a match between the expected data B and the pattern at the time when the strobe signal F is generated;
A defective signal H is generated for each channel. The fault signals for each channel are collected into one fault signal in the fault concentration circuit 3 to generate a combined fault signal.

By the way, an example of a speed test is the access item. When classifying this using the conventional method, the strobe and timing are reset for each grade, and the same test pattern is repeated multiple times. It is necessary to refer to the pass/fail judgment results, which has the disadvantage that the test takes a long time.

FIG. 2 is a principle diagram showing an example of the comparison/judgment method according to the present invention, where Fa and Fb are strobe signals set to different timing values. The level comparison result signal G is the output of the level comparison circuit 1, and is divided and fetched into two independent failure detection circuits and a failure concentration circuit for each strobe. Now, if we use the embodiment of the present invention to classify the speed of the access items cited above, we will set the timing settings of each strobe for each grade, run a test pattern, and detect the concentration failure. By referring to the results of each signal, there is an advantage that it is possible to determine which grade the integrated circuit belongs to by running one test pattern.

From this, it is clear that according to the present invention, the inspection time can be shortened.

[Brief explanation of drawings]

FIG. 1 shows an example of a comparison/judgment circuit of a conventional integrated circuit testing apparatus, and FIG. 2 is a principle diagram showing an example of a comparison/judgment circuit according to the present invention. In addition, in the figure, 1...level comparison circuit, 2
...Failure detection circuit, 3...Fault concentration circuit, A...
Defective detection enable signal, B...Expected data, C
...High level standard, D...Device output data,
E...Low level standard, F...Strobe signal, G
...Level comparison result signal, H...Failure signal for each channel, I...Failure concentration signal.

Claims (1)

[Claims] 1 In the comparison judgment circuit of an integrated circuit testing device,
It is equipped with a plurality of strobe signals and defect detection circuits corresponding to each of the signals, and compares expected data and measured data at different strobe timings to determine whether the data is good or bad, and the determination results are independently determined for each of the strobe signals. An integrated circuit testing device characterized in that it includes recognizable functionality.