JPH0161255B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monostable multivibrator circuit, and more particularly to a monostable multivibrator circuit that prohibits retriggering.

Conventionally, monostable multivibrator circuits have been widely used for time setting, etc., and produce an output for a set time from an input trigger pulse.
If the input trigger pulse width is wider than the set time,
If a plurality of trigger pulses are input within a set time, normal operation is not performed and a pulse with a pulse width different from the set time is output.

FIG. 1 is an example of a conventional monostable multivibrator circuit. 1 is a trigger input terminal, 2 is a timing circuit, 3 is a switching element, 7 is a capacitor, 4 is a resistor as a means for discharging the capacitor, and 5 is a resistor as a charging means to which a charging current is supplied from a power source 6. A comparator 9 produces an output when the voltage of the capacitor 7 exceeds the reference voltage 8. The timing circuit 2 opens the switching element 3 in response to a trigger pulse input to the trigger input terminal to start charging the capacitor 7 via the resistor 5, and when the voltage of the capacitor 7 exceeds the reference voltage 8, The resulting output from the comparator 9 closes the switching element 3 again and has the function of discharging the capacitor 7. In such a conventional monostable multivibrator circuit, from the start of the input trigger pulse, the capacitor 7
Charging is started, the voltage of the capacitor 7 rises directly or exponentially, and the time until the charging voltage of the capacitor 7 becomes equal to the reference voltage 8 becomes the set time of the monostable multivibrator circuit, that is, the pulse width. . This timing is switch element 3
This is the inversion of the output of timing circuit 2 that drives .

By the way, in this conventional monostable multivibrator circuit, when the first trigger pulse arrives and the second trigger pulse arrives after the capacitor 7 has performed the above-mentioned charge/discharge cycle, it operates normally. However, if the second trigger pulse arrives before the first charge/discharge cycle is completed, it will take longer for the charging voltage of the capacitor 7 to reach the reference voltage, and the pulse with a pulse width longer than the set time will be emitted. It will be output. Also, if the width of the first trigger pulse is longer than the set time of the monostable multivibrator circuit, the operation will be abnormal. In other words, the input trigger pulse of a monostable multivibrator circuit requires extensive restrictions on its pulse width and repetition frequency, and cannot be used as an input trigger signal that arrives arbitrarily.

SUMMARY OF THE INVENTION An object of the present invention is to provide a monostable multivibrator circuit capable of producing an output with a predetermined pulse width regardless of the successive intervals or pulse width of input trigger signals.

The monostable multivibrator according to the present invention has a capacitor and a voltage across the terminals of this capacitor that is
a comparator that generates an output when the reference voltage of the trigger signal is reached; a gate means that receives a trigger signal and controls whether or not to transmit the trigger signal; circuit means for switching the charging/discharging state of the capacitor in response to the output of the comparator, and switching the charging/discharging state of the capacitor again in response to the appearance of a trigger signal at the output of the gate means; a flip-flop for closing the gate means to inhibit transmission of a trigger signal regardless of charging and discharging conditions; and charging and discharging the capacitor by comparing the voltage across the terminals of the capacitor with a second reference voltage. control means for detecting that one cycle of the flip-flop is substantially completed and controlling the flip-flop to cause the flip-flop to open the gate means to permit transmission of the trigger signal.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which the same parts as in FIG. 1 are given the same numbers. Note that reference numeral 15 indicates the same conventional monostable multivibrator section as in FIG. A second comparator 10 has a second reference voltage 11 set to approximately 0 volts, and senses that the capacitor 7 is discharging. This resets the D-type flip-flop 12,
The Q output is set to high level and the gate 14 is operated. At this time, when a trigger pulse arrives from terminal 1, it passes through gate 14 and reaches timing circuit 2, and the monostable multivibrator circuit operates in the same manner as in FIG. Furthermore, the output of gate 14 is also applied to the clock input of flip-flop 12 mentioned above. Since the D input of flip-flop 12 is held high, this clock input inverts the Q output to a low level. Therefore, the gate 14 becomes non-conducting and its output becomes a low level regardless of the presence or absence of an input trigger pulse, and the conventional monostable multivibrator circuit 15
No preliminary pulses are applied to. Therefore, the monostable multivibrator circuit 15 will not malfunction. This prohibition of trigger input continues until the comparator 10 senses that the charge/discharge cycle of the monostable multivibrator circuit 15 is almost completed and resets the flip-flop 12.
That is, since retriggering is prohibited during most of the time when the monostable multivibrator circuit 15 is in operation, malfunctions can be avoided.

Note that if the reference voltage 11 is set to 0V, the judgment of the comparator may be incorrect due to noise and variations, so it may be set to about 0.1V, for example. If this is done, retriggering will not be inhibited when the voltage of the capacitor is between 0 and 0.1V, which may result in malfunction, but since the timing is small compared to the overall timing, there is little practical problem. If necessary, for example, timing circuit 2
By gating the reset input of the flip-flop 12 (not shown) with the output of the switching element 3 (i.e., the timing pulse for driving the switching element 3), it is possible to narrow the reset period and further reduce malfunctions.

The present invention is not limited to FIG. 2, but can be applied to all conventional monostable multivibrator circuits. Further, the flip-flop 12 is not limited to a D-type flip-flop, and even a T-type flip-flop operates in exactly the same way, so there is no problem.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional monostable multivibrator, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1...Input terminal, 2...Timing circuit, 3...
...Switching element, 4...Discharge means, 5, 6...
... Charging means, 7... Capacitor, 8, 11... Reference voltage, 9, 10... Comparing means, 12... Flip-flop circuit, 13... Voltage for setting high level, 14... Gate, 15... Conventional monostable multivibrator circuit.

Claims (1)

[Claims] 1 a capacitor, a comparator that generates an output when the voltage across the terminals of this capacitor reaches a first reference voltage, a gate means that receives a trigger signal and controls whether or not to transmit the trigger signal, and this gate circuit means for switching the charging and discharging states of the capacitor in response to the appearance of a trigger signal at the output of the means and switching the charging and discharging states of the capacitor again in response to the output of the comparator; a flip-flop for closing the gate means to inhibit transmission of the trigger signal regardless of the charging and discharging states of the capacitor in response to the occurrence of a trigger signal; detecting that one cycle of charging and discharging of the capacitor is substantially completed by comparing the flip-flop with a reference voltage of A monostable multivibrator comprising: a control means for controlling a monostable multivibrator;