JPH0161261B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a power-on reset circuit for preventing malfunctions when power is turned on or turned off in a digital circuit.

Digital circuits using integrated circuit elements, especially microcomputers, etc., need to be reset continuously for a period of time until the clock oscillator, such as a crystal, reaches stable oscillation even after the power is turned on and the voltage exceeds a predetermined allowable operating voltage. There are cases. A power-on reset circuit is a circuit that continues to reset the digital circuit etc. for a necessary period in such a case.

Prior Art An example of a conventional power-on reset circuit is shown in FIG. In other words, it is a circuit in which a series connection of a resistor R ₁₁ and a capacitor C ₁₁ is connected to the power supply Vcc, and a diode D ₂₁ is connected in parallel to the resistor R ₁₁ .
The charging voltage of _C11 is outputted from the terminal 1 and supplied to the target integrated circuit element 2 as a power-on reset signal Vo. The integrated circuit element 2 is supplied with power for operation by turning on the power supply Vcc, but remains in a reset state until a power-on reset signal higher than the reset release voltage V _B is applied, and then the reset release voltage V The reset is canceled by a power-on reset signal of _B or higher and normal operation is performed. Resistor R ₁₁ has a high resistance and may be included within the integrated circuit element 2 . In the conventional circuit described above, after the power supply Vcc is turned on, the capacitor _C11 is charged via the resistor _R11 , and when the charging voltage of the capacitor _C11 reaches a predetermined level _VB , the reset of the integrated circuit element 2 is released. Therefore, if the voltage rise at power-on is step-like as shown in FIG. 2a, the resistance R ₁₁ after power-on is
After a certain period of time t determined by the size of the capacitor _C11 , the power-on reset signal Vo exceeds a predetermined level of the reset release voltage _VB , and the reset can be released. On the other hand, the integrated circuit element 2 has
Immediately after the power is turned on, a voltage equal to or higher than the predetermined allowable operating voltage V _A is supplied. Therefore, integrated circuit element 2
is a certain period of time t after the allowable operating voltage V _A is applied
The reset will be canceled later. Also, when the power is turned off, the charge on capacitor _C11 is transferred to the diode
Since the integrated circuit element 2 is immediately discharged through _D21 , it is immediately reset and does not malfunction.

However, if the voltage rise and fall of the power supply Vcc has a slope as shown in Fig. 3a, the power-on reset signal Vo is set to the allowable operating voltage V _A as shown in Fig. 3b. The reset release voltage _VB may be reached before the reset release voltage VB is reached. In this case, the integrated circuit element 2 is released from reset while being supplied with a power supply voltage lower than the allowable operating voltage V _A during the period x shown in the figure, so there is a risk of malfunction. The same applies to the case of power-off. That is, the conventional power-on reset circuit shown in FIG. 1 may not serve its purpose.

In order to compensate for the above-mentioned drawbacks, a circuit configured as shown in FIG. 4 is also known. In this case, the first
The voltage of the capacitor C ₁₁ in the conventional circuit shown in the figure is passed through the Zener diode D ₁₁ to the transistor Q _11.
The emitter of transistor _Q11 is grounded, and the collector is connected to the power supply Vcc through a resistor. The collector of transistor Q ₁₁ is connected to the base of transistor Q ₂₁ , the emitter of transistor Q ₂₁ is grounded, and the collector is connected to power supply Vcc through a resistor. transistor
The collector voltage of _Q21 is output from terminal 1 as the power-on reset signal Vo. In the circuit described above, even when the rise of the power supply Vcc is sloped as shown in FIG. 5a, the charging voltage Vc of the capacitor _C11 rises as shown in _FIG . When the sum of the Zener voltage V _Z and the base-emitter voltage V _BE of the transistor Q ₁₁ reaches V _Z +V _BE , the transistor Q ₁₁ is turned on. Since the transistor Q ₂₁ turns off when the transistor Q ₁₁ turns on, if the above V _Z +V _BE is set equal to the allowable operating voltage V _A , the power-on reset signal Vo becomes as shown in c in the same figure. Be sure to power
Output is delayed after Vcc reaches _VA . However, this delay time t differs depending on the rise time of the power supply Vcc, and the longer the rise time, the shorter the delay time t becomes. Therefore, there is a drawback that the minimum value of the delay time t cannot be guaranteed. Furthermore, when the power is turned off, the capacitor C ₁₁ starts discharging when the power supply voltage drops to V _Z + V _BE − V _D (V _D is the forward voltage of the diode D ₂₁ ), that is, V _A − V _D. Therefore, the power supply Vcc is within the allowable operating voltage.
Even after the voltage drops below V _A , the transistor Q ₁₁ continues to be on for a while (during the period x). During this period x, the transistor _Q21 is off, so the power-on reset signal Vo is higher than the reset release voltage _VB as shown in FIG. 5c. That is, there is a drawback that the reset remains released during period x, making it impossible to prevent malfunctions of the integrated circuit.

OBJECT OF THE INVENTION The object of the invention is to solve the above-mentioned conventional drawbacks and
To provide a power-on reset circuit that can release the reset after a certain period of time after the power supply voltage reaches the allowable operating voltage of an integrated circuit, and can reset immediately when the power supply voltage falls below the allowable operating voltage. It is in.

Structure of the Invention The reset circuit of the present invention includes a first switching circuit whose one end is grounded and which is turned on by a power supply voltage of a certain value or more that is input through a Zener diode, and a reset circuit connected in series between the first switching circuit and the power supply. A series connection circuit of a connected capacitor, a resistor, and a first diode, a second switching circuit that turns on when the voltage across the capacitor exceeds a certain value, and turns on and off by turning on and off the first switching circuit. and a second diode having a cathode connected to one end of the capacitor and an anode grounded,
A series connection circuit of the second switching circuit, the third switching circuit, and an output resistor is connected between a power source and ground, and a power-on reset signal is output from one end of the output resistor.

Incidentally, if the voltage of the capacitor is applied to the control input of the second switching circuit via the second Zener diode, it is easy to lengthen the certain period of time until reset.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 6 is a circuit diagram showing one embodiment of the present invention. That is, a series connection circuit consisting of a capacitor _C1 , a resistor _R2 , a first diode _D3 , and the collector-emitter of a transistor _Q1 is connected between the power supply Vcc and the ground. The base of the transistor Q ₁ is connected to the power supply through the resistor R ₁ and the first Zener diode D ₁
Connected to Vcc. The sum of the Zener voltage V _Z1 of the first Zener diode D ₁ and the base-emitter voltage V _BE of the transistor Q ₁ is the allowable operating voltage V _A
is set equal to . Therefore, transistor _Q1 is turned on when the voltage of power supply Vcc exceeds a certain allowable operating voltage _VA . In this embodiment, a first switching circuit is composed of a transistor Q ₁ , a resistor R ₁ , and a Zener diode D ₁ .

Further, the emitter of the transistor Q ₂ is connected to the power supply Vcc, and the base of the transistor Q ₂ is connected to the connection point between the capacitor C ₁ and the resistor R ₂ via the second Zener diode D ₂ . Transistor Q ₃ has its emitter connected to the collector of transistor Q ₂ , its collector connected to ground via output resistor R ₄ , and its base connected to the collector of transistor Q ₁ through resistor R ₃ . Also connect the cathode of the second diode D ₄ to the capacitor C ₁ ,
The anode is grounded. The above transistor Q ₂ is a second switching circuit, and the transistor Q ₃
is the third switching circuit. The second switching circuit, i.e. the transistor Q ₂ , remains off until the charging voltage Vc of the capacitor C ₁ reaches the sum of the Zener voltage V _Z2 of the second Zener diode D ₂ and the base-emitter voltage V _BE of the transistor Q ₂ . , and turns on when the voltage is higher than the above voltage. Third
The switching circuit of transistor _Q3 is
When the transistor Q ₁ is on, it is in an on state or in a state that can be turned on, and when the transistor Q ₁ is off, it is in an off state. diode
D ₃ is the polarity that blocks the base current of transistor Q ₃ . Further, the second and third switching circuits and the output resistor _R4 are connected in series, and the power-on reset signal Vo is output from one end of the output resistor _R4 through the terminal 1. It is at a high level only when both the second and third switching circuits are on, and it is at a low level when either one of the switches is off.

Next, the operation of this embodiment will be explained with reference to FIGS. 6 and 7. Figure 7a is the power supply Vcc
b is the charging voltage Vc of capacitor _C1 ,
Figure c is a time chart showing the power-on reset signal Vo. First, turn on the power.
When the voltage Vcc increases as shown in FIG. 7a and reaches a certain allowable operating voltage V _A , the first Zener diode becomes conductive and transistor Q ₁ is turned on.
That is, the first switching circuit is turned on.
This starts charging capacitor _C1 ,
The charging voltage Vc of capacitor _C1 increases as shown in FIG. 7b. When the voltage reaches a certain value, which is the sum of the Zener voltage VZ2 of the second Zener diode _D2 and the base-emitter voltage _VBE of the transistor _Q2, the transistor _Q2, ie, the second switching circuit, is turned on. On the other hand, since the base of transistor _Q3 has already been grounded by the first switching circuit, the third switching circuit can be turned on, and the power supply Vcc is connected to the output resistor through the second and third switching circuits. _R4 , and a high-level power-on reset signal Vo as shown in FIG. 7c is output from terminal 1.
The delay time t until the voltage of the capacitor _C1 turns on the second switching circuit depends on the rising speed of the power supply Vcc, but it is approximately the same as the capacitance of the capacitor _C1 , the resistance value of the resistor _R2 , and the second Zener diode. It is determined by the Zener voltage V _Z2 of D ₂ , etc.
This delay time is minimum when the power supply Vcc is applied in a stepwise manner. Therefore, by setting this minimum delay time t ₀ to a predetermined value, a delay time greater than or equal to t ₀ can be obtained. That is, the integrated circuit (not shown) will not malfunction because it will continue to be reliably reset for a certain delay time _t0 after being supplied with a power supply voltage equal to or higher than the allowable operating voltage _VA . Furthermore, when the power is turned off, when the voltage of the power supply Vcc drops to the allowable operating voltage V _A as shown in Figure 7a, the transistor _Q1 is turned off and the base current of the transistor _Q3 is cut off. ₃ is also off. Therefore, the power-on reset signal Vo immediately goes to a low level as shown in FIG. This completely prevents malfunctions of the integrated circuit. On the other hand, transistor Q ₂ has a power supply Vcc of V _Z2
It remains on until it drops to +V _BE -V _D (V _D is the forward voltage of diode _D4 ), and then turns off. Also, the charge on capacitor C ₁ is transferred to diode D ₄
The voltage Vc of the capacitor _C1 becomes 0 as shown in b of the same figure. Figure d shows the on/off states of the transistors _Q1 to _Q3 during the above-described operation.

FIG. 8 shows a modification of the above embodiment, and is a circuit in which resistors R ₅ to R ₇ are connected between the emitter bases of transistors Q ₁ to _{Q 3} shown in FIG. 6, respectively. In this case, the transistors Q 1 to _{Q 3 are prevented from being turned on due to the leakage current of the first Zener diode D 1 , the second Zener diode D 2 or the transistor Q 1 , and the switching} operation is made more reliable. It has the advantage of

FIG. 9 is a circuit diagram showing a second embodiment of the present invention. This is a circuit in which a resistor _R8 is inserted in series with the transistor _Q3 and resistor _R4 in FIG. In this case, if the resistor R ₈ is selected so as to ensure that the level of terminal 1 after the reset is released is the TTL "1" level, the power consumption of the transistors Q ₂ and Q ₃ after the reset is released can be reduced.

FIG. 10 is a circuit diagram showing a third embodiment of the present invention, which differs from FIG. 6 in that it does not include the second Zener diode _D2 . It can be applied when the time that the power supply must continue to be reset after reaching the permissible operating voltage is relatively short. The same effect can be obtained even if the second Zener diode _D2 in FIGS. 8 and 9 is deleted.

Effects of the Invention As described above, in the present invention, charging of the series connection circuit of a capacitor and a resistor is started by the first switching circuit that turns on the power supply when the voltage exceeds the allowable operating voltage, and the capacitor is turned on when the voltage exceeds a certain level. The second switching circuit is turned on when the battery is charged, and the first switching circuit is controlled to be turned on or turned on when the first switching circuit is turned on.
The third circuit is turned off by turning off the switching circuit of
The switching circuit has a configuration in which the second and third switching circuits and the output resistor are connected in series between the power supply and the ground, so that when the power is turned on, a certain period of time elapses after the power supply reaches the allowable operating voltage. There is an effect that the above-mentioned reset is reliably continued, and furthermore, when the power is turned off, the reset can be performed immediately when the voltage drops to the allowable operating voltage.
In other words, it is possible to reliably prevent malfunctions of the digital circuit when power is turned on and off.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a conventional reset circuit, Figs. 2 and 3 are waveform diagrams of various parts showing an example of the operation of the above conventional example, and Fig. 4 is a circuit diagram showing another conventional example. , FIG. 5 is a waveform diagram showing the waveforms of various parts of the conventional example shown in FIG. 4, and FIG.
FIG. 7 is a time chart showing waveforms, operations, etc. of each part of the first embodiment,
FIG. 8 is a circuit diagram showing a modification of the first embodiment, and FIGS. 9 and 10 are circuit diagrams showing second and third embodiments of the present invention, respectively. In the figure, 1...Terminal, 2...Integrated circuit element, _Q1 to _Q3 ...Transistor, D1...First Zener diode, _D2 ... _Second Zener diode, _D3 , _D4 ... …Diode, C ₁ … Capacitor, R ₁ ~ _{R 3} … Resistor, R ₄ … Output resistance, R ₅ ~
R ₈ ...Resistor, Vcc...Power supply, Vc...Capacitor charging voltage, Vo...Power-on reset signal,
V _A ... Allowable operating voltage, V _Z1 , V _Z2 ... Zener voltage of the first and second Zener diodes, V _B
...Reset release voltage, V _BE ...Transistor base-emitter voltage, V _D ...Diode forward voltage.

Claims (1)

[Claims] 1. A first Zener diode _D1 to which a power supply voltage is substantially applied via a resistor circuit, and one end connected to a common potential when the power supply voltage exceeds the Zener voltage of this Zener diode. a first switching circuit Q ₁ conductive to the capacitor C ₁ , one end of which is connected to a power supply, a resistor R ₂ and a first switching circuit connected in series between the first switching circuit and the other end of the capacitor; a series-connected circuit of diodes _D3 , a second diode _D4 connected in a direction opposite to the applied voltage between one end of the capacitor and a common potential _; a second switching circuit Q ₂ which conducts when the voltage across it is above a certain value, and which conducts and opens in accordance with the conduction and opening of the first switching circuit, and one end of which is connected to the other end of the second switching circuit. a third switching circuit _Q3 , an output resistor _R4 connected between the other end of the third switching circuit and a common potential, and an output terminal to which the voltage across the output resistor is connected. Equipped with power-on reset circuit. 2 The second switching circuit has a second Zener diode inserted in series in its control input path.
A power-on reset circuit as claimed in claim 1 comprising _D2 .