JPH0161271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory drive circuit used in a facsimile device or the like that drives a plurality of buffer memories at a plurality of speeds to temporarily store image information.

FIG. 1 shows an example of a conventional memory drive circuit.
In the figure, 1 is 1 from 1 line of data XIDT
1-line all-white detection circuit that detects all white lines;
2 and 3 are storage circuits for storing data XIDT (hereinafter referred to as buffer memories); 4 and 5 are selection circuits for selecting address outputs of address counters 6 and 7 and read/write clocks for buffer memories 2 and 3; 6; , 7 are address counters that operate at high and low speeds, respectively, and 8 is a data selector for selectively outputting image information data from the buffer memory 2 or 3.

In the image information memory control circuit having such a configuration, one line of image information data XIDT is written into one of the buffer memories 2 and 3, for example, the buffer memory 2. At this time, the selection circuit 5 selects the high-speed address counter 6, so
XIDT is written to buffer memory 2 at high speed. On the other hand, if data is stored in the buffer memory 3, the data selector 8 is connected to the position indicated by the dotted line, so that data is read from the buffer memory 3 during this time. At this time, since the selection circuit 4 selects the low-speed address counter 7, this reading is performed at low speed.

Next, when a predetermined period of time has elapsed, the data selector 8
is switched to the position indicated by the solid line, and the XIDT written in the buffer memory 2 is sent out as transmission data XODT via the data selector 8. Since the selection circuit 5 selects the low-speed address counter 7, reading from the buffer memory 2 is performed at a low speed matching the transmission speed of the telephone line. While data is being read from buffer memory 2, data is being written to the other buffer memory 3 at high speed. Similarly, while one buffer memory is being written, one line of data is read from the other buffer memory, and this process is repeated.

In addition, two buffer memories are provided in this way,
The reason why one line of data XIDT is written at high speed is to perform some processing after one line of image information is read out from the scanning device. For example, when the one-line all-white detection circuit 1 detects that one line is all white, the process can be skipped and the next line processed.

In such a conventional device, selection circuits 4 and 5 are required for both buffer memories 2 and 3, which not only complicates the circuit but also increases manufacturing cost.

An object of the present invention is to fix the control speed of any one of a plurality of buffer memories, thereby reducing the number of selection circuits for selecting memory addresses, read clocks, write clocks, etc., and reducing costs. An object of the present invention is to provide a highly reliable memory drive circuit.

First, the principle of the present invention will be explained. In the figure,
10 and 11 are first and second buffer memories each storing one line of data XIDT; 12
13 is a selection circuit for selecting a high-speed address counter and a low-speed address counter; 14 is a high-speed address counter;
indicates a slow address counter.

Now, if one line of data XIDT is input to the first buffer memory 10, then the data
XIDT is written at high speed by the high speed address counter 13. Next, the first buffer memory 1
0 is read out at high speed by the high speed address counter 13, and the aforementioned XIDT is transferred to the second buffer memory 11. At this time, since the selection circuit 12 selects the high-speed address counter 13, the second buffer memory 11 writes the data XIDT at high speed.

Next, the selection circuit 12 selects the low speed address counter 14 to control the address, read and write clocks. Therefore, data is read from the second buffer memory 11 at a low speed matching the transmission speed of the telephone line. The read image information data XODT is sent to the modulator. Meanwhile, in the first buffer memory 10, the next line of data XIDT is written at high speed during this period. Depending on the content of the line image information data, several lines are written at high speed.

As described above, since writing and reading from the first buffer memory 10 can be performed at high speed, the selection circuit only needs to be provided for the second buffer memory, and there is an advantage that only one selection circuit is required.

FIG. 3 shows an embodiment of the invention. This embodiment is suitable for reception by a facsimile device, and numerals 15 and 16 in the figure represent first and second data selectors, respectively. Note that the symbols other than these indicate the same or equivalent items as in FIG. 2.

The operation of this embodiment will be explained below. First, the operation in the case of transmission will be explained. At first, the first
and the second data selector is connected to the position indicated by the solid line in the figure, and the 1
The line image information data is stored in the first buffer memory 1.
0 is written at high speed by the high speed address counter 13. Next, since the first and second data selectors 15 and 16 are interlocked, they are both connected to the positions indicated by dotted lines. At this time, selection circuit 1
2 selects the high-speed address counter 13, so the information written in the first buffer memory 10 is read out at high speed and written into the second buffer memory 11 at high speed.

In the next stage, the first and second data selectors 15, 16 are connected again to the original solid line positions. At this time, the selection circuit 12 selects the low-speed address counter 14. Therefore, data is read out from the second buffer memory 11 at a speed that matches the transmission speed of the telephone line, and is sent to the modulator as transmission data XODT. On the other hand, the first buffer memory 10 is operated at high speed by a high-speed address counter 13, and the next line of image information data is stored in the first buffer memory 10 through the data selector 15 at high speed.

By repeating the above operations, image information data is continuously transmitted.

Next, the operation in the case of reception will be explained. Initially, the first and second data selectors 15, 16
are connected to the solid line locations shown. Now, suppose that image information data RIDT is sent from a telephone line via a demodulator, this data
RIDT is stored in the second buffer memory 11. At this time, since the selection circuit 12 selects the low-speed address counter 14, the second buffer memory 11 operates at a low speed matching the transmission speed of the telephone line.

Thereafter, at an appropriate time, the first and second data selectors 15 and 16 are connected to the positions indicated by dotted lines in the figure. At this time, the selection circuit 12 selects the high-speed address counter 13. Therefore, the second
The data stored in the first buffer memory 11 is read out at high speed and written to the first buffer memory 10 via the data selector 15 at high speed.

In the next phase, the first and second data selectors 15, 16 are returned to their original positions indicated by solid lines. The data stored in the first buffer memory 10 is transferred to a high-speed address counter 10.
is read out at high speed. This read data is sent to the printer as received image information data RODT. At this time, the second buffer memory 1
1, image information data is written at low speed.

In this way, in the embodiment described above, although there is only one selection circuit, transmission and reception can be performed efficiently.

As described above, according to the memory drive circuit of the present invention, the number of selection circuits for memory address and read/write clocks can be reduced by one compared to the conventional one, so the effect is low cost and high reliability. There is.

Further, even though there is only one selection circuit, there is an effect that transmission and reception can be carried out efficiently.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of a conventional buffer memory driving circuit, and FIGS. 2 and 3 are functional block diagrams of buffer memory driving circuits showing the principle and one embodiment of the present invention, respectively. 10...first buffer memory, 11...second
buffer memory, 12... selection circuit, 13...
High-speed address counter, 14...low-speed address counter, 15, 16... data selector.

Claims (1)

[Claims] 1. A first changeover switch that switches between the first input terminal and the output of the second buffer memory;
a first buffer memory to which the input side of the first selector switch is connected; a second selector switch that selects by switching between a second input terminal and the output of the first buffer memory; the second buffer memory to which its input side is connected; a first address counter with high-speed operation that controls the operation of the first buffer memory; a second address counter with low-speed operation; and the first and second address counters. one selection circuit that selects one of the buffer memory and controls the operation of the second buffer memory according to the selected address counter, and when transmitting data, the first input terminal → the first buffer memory → the second buffer memory is selected. The selection circuit controls the first and second changeover switches so that data is transferred in the order of buffer memories, and controls the first address counter when data is transferred from the first buffer memory to the second buffer memory. , when data is transferred from the second buffer memory to the telephone line, the second address counter is selected; on the other hand, when data is received, the data is transferred from the second input terminal to the second buffer memory to the first buffer memory. The selection circuit controls the first and second changeover switches so that the transfer is performed, and also selects the second address counter when data is transferred from the second input terminal to the second buffer memory. 2 buffer memory → 1st
1. A memory drive circuit for a facsimile device, wherein the first address counter is selected when transferring a buffer memory.