JPH0164200U - - Google Patents
Info
- Publication number
- JPH0164200U JPH0164200U JP1987159511U JP15951187U JPH0164200U JP H0164200 U JPH0164200 U JP H0164200U JP 1987159511 U JP1987159511 U JP 1987159511U JP 15951187 U JP15951187 U JP 15951187U JP H0164200 U JPH0164200 U JP H0164200U
- Authority
- JP
- Japan
- Prior art keywords
- potential
- read
- mos transistor
- inverter
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013500 data storage Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims 2
- 239000003990 capacitor Substances 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の実施例を示す回路図、第２図
は従来例を示す回路図である。
６…データ記憶回路、７…第１ＭＯＳトランジ
スタ、９…第２ＭＯＳトランジスタ、１２…イン
バータ、１０…第３ＭＯＳトランジスタ、１１…
第４ＭＯＳトランジスタ、１３…遅延回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 6... Data storage circuit, 7... First MOS transistor, 9... Second MOS transistor, 12... Inverter, 10... Third MOS transistor, 11...
4th MOS transistor, 13...delay circuit.
Claims (1)
ＭＯＳトランジスタがデータ読み出しノードと第
１電位間に並列あるいは直列接続されて成るデー
タ記憶回路と、前記データ読み出しノードを第２
の電位にプリチヤージするためにプリチヤージ信
号で制御される第２ＭＯＳトランジスタと、前記
データ読み出しノードが入力に接続されデータ読
み出しノードの電位を検出するインバータとを備
えたリードオンリメモリに於いて、前記プリチヤ
ージ信号を入力するインバータ及びコンデンサで
遅延された信号と遅延前の信号を入力する論理ゲ
ートにより、プリチヤージ信号の終端を遅延する
遅延回路と、前記データ読み出しノードと第２の
電位間に直列接続され、前記データ読み出しノー
ドの電位を検出するインバータの出力がゲートに
接続された第３ＭＯＳトランジスタ、及び、前記
遅延回路の出力がゲートに印加された第４ＭＯＳ
トランジスタを設けたことを特徴とするリードオ
ンリメモリ。 a plurality of first gates having address signals applied to their gates;
A data storage circuit including a MOS transistor connected in parallel or series between a data read node and a first potential;
In the read-only memory, the read-only memory includes a second MOS transistor controlled by a precharge signal to precharge to a potential of the precharge signal, and an inverter to which the data readout node is connected to an input and detects the potential of the data readout node. a delay circuit that delays the end of the precharge signal by an inverter that inputs the signal delayed by the capacitor and a logic gate that inputs the signal before the delay; and a delay circuit that delays the termination of the precharge signal, and the a third MOS transistor whose gate is connected to the output of an inverter that detects the potential of the data read node; and a fourth MOS transistor whose gate is connected to the output of the delay circuit.
A read-only memory characterized by the provision of a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987159511U JPH0164200U (en) | 1987-10-19 | 1987-10-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987159511U JPH0164200U (en) | 1987-10-19 | 1987-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0164200U true JPH0164200U (en) | 1989-04-25 |
Family
ID=31440788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987159511U Pending JPH0164200U (en) | 1987-10-19 | 1987-10-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0164200U (en) |
-
1987
- 1987-10-19 JP JP1987159511U patent/JPH0164200U/ja active Pending
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