JPH0165553U - - Google Patents
Info
- Publication number
- JPH0165553U JPH0165553U JP1987160239U JP16023987U JPH0165553U JP H0165553 U JPH0165553 U JP H0165553U JP 1987160239 U JP1987160239 U JP 1987160239U JP 16023987 U JP16023987 U JP 16023987U JP H0165553 U JPH0165553 U JP H0165553U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- horizontal synchronization
- circuit
- synchronization signal
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims 3
- 239000002131 composite material Substances 0.000 claims 2
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第１図ないし第３図はこの考案の水平同期回路
の１実施例を示し、第１図はブロツク図、第２図
ａ，ｂはゲートパルス発生回路の動作説明用のタ
イミングチヤート、第３図ａ〜ｃは垂直帰線期間
のゲート回路の動作説明用のタイミングチヤート
、第４図ａ〜ｃは従来の水平同期回路の動作説明
用のタイミングチヤートである。
１……ＰＬＬ回路、２……ＶＣＯ、３……ゲー
ト回路、４……ゲートパルス発生回路、７……分
周器。
1 to 3 show one embodiment of the horizontal synchronization circuit of this invention, FIG. 1 is a block diagram, FIGS. 2a and 2b are timing charts for explaining the operation of the gate pulse generation circuit, and FIG. 4a to 4c are timing charts for explaining the operation of the gate circuit during the vertical retrace period, and FIGS. 4a to 4c are timing charts for explaining the operation of the conventional horizontal synchronization circuit. 1... PLL circuit, 2... VCO, 3... Gate circuit, 4... Gate pulse generation circuit, 7... Frequency divider.
Claims (1)
どの映像機器に設けられ、複合映像信号から分離
された入力水平同期信号をゲート処理して同期Ａ
ＦＣ用のＰＬＬ回路に入力し、該ＰＬＬ回路によ
り、前記入力水平同期信号にもとづいて電圧制御
発振器の発振周波数を制御するとともに、前記発
振器の発振信号を分周し、前記入力水平同期信号
に同期した内部水平同期信号を生成して出力する
水平同期回路において、 前記ＰＬＬ回路の前段に設けられ、ゲートパル
スのパルス幅に比例して信号通過期間が可変され
る不要信号排除用のゲート回路と、 前記発振信号の分周信号と前記複合映像信号の
垂直同期信号に同期した信号とにもとづき、垂直
帰線期間の少なくとも前縁側の一部の期間のパル
ス幅が水平同期信号抽出用の規定パルス幅より幅
広に可変される前記ゲートパルスを形成して出力
するゲートパルス発生回路とを備えた水平同期回
路。[Claims for Utility Model Registration] Synchronization A is provided in video equipment such as television receivers and image display devices, and performs gate processing on the input horizontal synchronization signal separated from the composite video signal.
The signal is input to a PLL circuit for FC, and the PLL circuit controls the oscillation frequency of the voltage controlled oscillator based on the input horizontal synchronization signal, and divides the oscillation signal of the oscillator to synchronize with the input horizontal synchronization signal. a horizontal synchronization circuit that generates and outputs an internal horizontal synchronization signal, the gate circuit being provided before the PLL circuit and having a signal passing period variable in proportion to the pulse width of the gate pulse for eliminating unnecessary signals; Based on the frequency-divided signal of the oscillation signal and the signal synchronized with the vertical synchronization signal of the composite video signal, the pulse width of at least a portion of the leading edge side of the vertical blanking period is a specified pulse width for extracting the horizontal synchronization signal. A horizontal synchronization circuit comprising a gate pulse generation circuit that forms and outputs the gate pulse whose width is varied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16023987U JPH0523018Y2 (en) | 1987-10-20 | 1987-10-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16023987U JPH0523018Y2 (en) | 1987-10-20 | 1987-10-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0165553U true JPH0165553U (en) | 1989-04-26 |
| JPH0523018Y2 JPH0523018Y2 (en) | 1993-06-14 |
Family
ID=31442131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16023987U Expired - Lifetime JPH0523018Y2 (en) | 1987-10-20 | 1987-10-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0523018Y2 (en) |
-
1987
- 1987-10-20 JP JP16023987U patent/JPH0523018Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0523018Y2 (en) | 1993-06-14 |
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