JPH0412763U - - Google Patents
Info
- Publication number
- JPH0412763U JPH0412763U JP5351990U JP5351990U JPH0412763U JP H0412763 U JPH0412763 U JP H0412763U JP 5351990 U JP5351990 U JP 5351990U JP 5351990 U JP5351990 U JP 5351990U JP H0412763 U JPH0412763 U JP H0412763U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- gate signal
- horizontal
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Synchronizing For Television (AREA)
- Color Television Systems (AREA)
- Transforming Electric Information Into Light Information (AREA)
- Processing Of Color Television Signals (AREA)
Description
第１図は本考案の一実施例のブロツク構成図、
第２図はその信号波形図、第３図は従来の水平Ｐ
ＬＬ回路のブロツク構成図である。
１，１２……入力端子、２，８……位相比較器
、３，９……ローパスフイルタ（ＬＰＦ）、４…
…８ｆｓｃ電圧制御型発振器（８ｆｓｃＶＣＯ）
、５……1/4分周器、６……1/455分周器、７……
出力端子、１０……２ｆＨ電圧制御型発振器（２
ｆＨＶＣＯ）、１１……1/2分周器、１３……垂
直ゲート信号生成回路、１４……水平ゲート信号
生成回路、１５……ＮＯＲ回路、１６……ＯＲ回
路。
FIG. 1 is a block diagram of an embodiment of the present invention.
Figure 2 is the signal waveform diagram, Figure 3 is the conventional horizontal P
FIG. 3 is a block diagram of the LL circuit. 1, 12... Input terminal, 2, 8... Phase comparator, 3, 9... Low pass filter (LPF), 4...
...8fsc voltage controlled oscillator (8fscVCO)
, 5...1/4 frequency divider, 6...1/455 frequency divider, 7...
Output terminal, 10...2fH voltage controlled oscillator (2
fHVCO), 11...1/2 frequency divider, 13...Vertical gate signal generation circuit, 14...Horizontal gate signal generation circuit, 15...NOR circuit, 16...OR circuit.
Claims (1)
号を生成する垂直ゲート信号生成回路と、 パルス幅が略水平帰線期間である水平ゲート信
号を生成する水平ゲート信号生成回路と、 前記垂直ゲート信号と前記水平ゲート信号とが
供給されるＮＯＲ回路と、 前記ＮＯＲ回路の出力信号と、映像信号から同
期分離された複合同期信号とが供給され、水平同
期信号を出力するＯＲ回路と、 所定クロツク信号生成回路を備えたＰＬＬ回路
であつて、前記ＯＲ回路の出力信号が供給されて
所定クロツク信号を出力するＰＬＬ回路とより構
成したことを特徴とするクロツク信号発生回路。[Claims for Utility Model Registration] A vertical gate signal generation circuit that generates a vertical gate signal whose pulse width is approximately the vertical blanking period, and a horizontal gate signal that generates a horizontal gate signal whose pulse width is approximately the horizontal blanking period. a generation circuit; a NOR circuit to which the vertical gate signal and the horizontal gate signal are supplied; an output signal of the NOR circuit and a composite synchronization signal synchronously separated from the video signal are supplied, and a horizontal synchronization signal is output. 1. A clock signal generation circuit comprising: an OR circuit, and a PLL circuit provided with a predetermined clock signal generation circuit, the PLL circuit being supplied with an output signal of the OR circuit and outputting a predetermined clock signal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5351990U JPH0412763U (en) | 1990-05-22 | 1990-05-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5351990U JPH0412763U (en) | 1990-05-22 | 1990-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0412763U true JPH0412763U (en) | 1992-01-31 |
Family
ID=31574775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5351990U Pending JPH0412763U (en) | 1990-05-22 | 1990-05-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0412763U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08111789A (en) * | 1994-09-28 | 1996-04-30 | Internatl Business Mach Corp <Ibm> | Method and equipment for horizontal synchronizing signal stabilization |
-
1990
- 1990-05-22 JP JP5351990U patent/JPH0412763U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08111789A (en) * | 1994-09-28 | 1996-04-30 | Internatl Business Mach Corp <Ibm> | Method and equipment for horizontal synchronizing signal stabilization |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6333280U (en) | ||
| JP2600714Y2 (en) | Circuit for generating carrier signal and test signal of RF modulator | |
| JPH024363U (en) | ||
| JPH0466876U (en) | ||
| JPH0467824U (en) | ||
| JPH01117183U (en) | ||
| JPH0370431U (en) | ||
| JPS62152579U (en) | ||
| JPH0467823U (en) | ||
| JPH0238881U (en) | ||
| JPS611978U (en) | Timing signal generation circuit | |
| JPS6258962U (en) | ||
| JPS6293880U (en) | ||
| JPS62146362U (en) | ||
| JPH0444692U (en) | ||
| JPH03117946U (en) | ||
| JPH02150884U (en) | ||
| JPH03103679U (en) | ||
| JPS61154072U (en) | ||
| JPH01171381A (en) | Synchronizing signal reproducing circuit | |
| JPS62155528U (en) | ||
| JPH02134788U (en) | ||
| JPH03117945U (en) | ||
| JPS61111258U (en) | ||
| JPH03123327U (en) |