JPH0166018U

JPH0166018U -

Info

Publication number: JPH0166018U
Application number: JP1987161885U
Authority: JP
Priority date: 1987-10-22
Filing date: 1987-10-22
Publication date: 1989-04-27

Description

[Brief explanation of the drawing]

第１図は本考案の２相エンコーダ回路の一実施
例を示す回路図、第２図〜第４図は本考案の説明
に供する図である。１〜３……入力端子、４〜７……Ｄ型フリツプ
フロツプ回路、８〜１０……イクスクルーシブ・
オア回路、１１，１２……ノア回路、１３……ア
ツプダウンカウンタ。 FIG. 1 is a circuit diagram showing an embodiment of a two-phase encoder circuit of the present invention, and FIGS. 2 to 4 are diagrams for explaining the present invention. 1-3...Input terminal, 4-7...D flip-flop circuit, 8-10...Exclusive
OR circuit, 11, 12...NOR circuit, 13...Up-down counter.

Claims

[Scope of claim for utility model registration] “H” according to the movement (rotation) of a moving body (rotating body)
"state" and "L" state are alternately repeated, and first and second detection signals whose phases are shifted by 90 degrees from each other are input, and based on the first and second detection signals, the mobile object (
a two-phase encoder circuit for determining the movement (rotation) status of a rotating body), and a first signal capture means that captures the first detection signal in synchronization with a clock signal and sequentially outputs the first capture signal. and second signal capturing means for capturing the second detection signal in synchronization with the clock signal and sequentially outputting the second captured signal; a first delay means for outputting a first delayed signal delayed by the captured signal; and a second delay means for outputting a second delayed signal delayed by the predetermined time T from the second captured signal; a pulse signal output means for outputting a pulse synchronized with each state inversion of the first capture signal and the second capture signal from at least the first and second capture signals; and the first delayed signal. The state of the pulse is inverted in synchronization with each state inversion of the second acquisition signal, and the state inversion precedes the pulse synchronized with the state inversion of the first acquisition signal, and the state of the pulse is inverted in synchronization with each state inversion of the second acquisition signal. up-down signal output means for outputting an up-down signal whose state reversal is delayed with respect to the pulse synchronized with the state reversal of the signal; and a means for counting the number of pulses of the pulse signal;
A two-phase encoder circuit comprising an up-down counter that performs up-counting or down-counting according to each state of the up-down signal.