JPH0167819U - - Google Patents
Info
- Publication number
- JPH0167819U JPH0167819U JP1987162481U JP16248187U JPH0167819U JP H0167819 U JPH0167819 U JP H0167819U JP 1987162481 U JP1987162481 U JP 1987162481U JP 16248187 U JP16248187 U JP 16248187U JP H0167819 U JPH0167819 U JP H0167819U
- Authority
- JP
- Japan
- Prior art keywords
- input
- amplifier circuit
- signal
- fet
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000005236 sound signal Effects 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図および第２図はこの考案の実施例を示す
回路図である。第３図乃至第６図は従来例を示す
もので、第３図および第４図は、入力素子として
トランジスタを用いた増幅器をＦＥＴを用いた増
幅器とを並列接続、および直列接続した場合を示
す回路図、第５図は入力素子とし複数個のＦＥＴ
を並列接続した場合を示す回路図、第６図は入力
素子としてトランジスタとＦＥＴを切換えて使用
する場合を示す回路図である。
主要部分の符号の説明、ＩＮ：オーデイオ信号
入力端子、ＯＵＴ：オーデイオ信号出力端子、Ｑ
１〜Ｑ４：入力素子として機能するトランジスタ
、Ｑ５：入力素子として機能するＦＥＴ、Ｓ１：
入力素子選択用のスイツチ。
1 and 2 are circuit diagrams showing an embodiment of this invention. 3 to 6 show conventional examples, and FIGS. 3 and 4 show cases in which an amplifier using a transistor as an input element and an amplifier using an FET are connected in parallel and in series. The circuit diagram, Figure 5, shows multiple FETs as input elements.
FIG. 6 is a circuit diagram showing a case where transistors and FETs are used as input elements by switching between them. Explanation of symbols of main parts, IN: audio signal input terminal, OUT: audio signal output terminal, Q
1 to Q4: Transistor functioning as an input element, Q5: FET functioning as an input element, S1:
Switch for input element selection.
Claims (1)
Ｔと、このＦＥＴの出力信号またはＦＥＴへの入
力信号のいずれか一方を選択してトランジスタへ
入力するスイツチ回路とを備え、このスイツチ回
路を信号源インピーダンスの大小が著しく異なる
入力信号に対応して切換えるように構成したこと
を特徴とする入力素子選択型増幅回路。 FE connected to the first stage of signal input of the amplifier circuit
T, and a switch circuit that selects either the output signal of this FET or the input signal to the FET and inputs it to the transistor, and the switch circuit is adapted to handle input signals having significantly different signal source impedances. An input element selection type amplifier circuit characterized in that the input element selection type amplifier circuit is configured to switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987162481U JPH0167819U (en) | 1987-10-26 | 1987-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987162481U JPH0167819U (en) | 1987-10-26 | 1987-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0167819U true JPH0167819U (en) | 1989-05-01 |
Family
ID=31446347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987162481U Pending JPH0167819U (en) | 1987-10-26 | 1987-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0167819U (en) |
-
1987
- 1987-10-26 JP JP1987162481U patent/JPH0167819U/ja active Pending
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