JPH01110524U - - Google Patents

Info

Publication number
JPH01110524U
JPH01110524U JP638688U JP638688U JPH01110524U JP H01110524 U JPH01110524 U JP H01110524U JP 638688 U JP638688 U JP 638688U JP 638688 U JP638688 U JP 638688U JP H01110524 U JPH01110524 U JP H01110524U
Authority
JP
Japan
Prior art keywords
bias voltage
transistor
input
pair
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP638688U
Other languages
Japanese (ja)
Other versions
JPH0638492Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988006386U priority Critical patent/JPH0638492Y2/en
Publication of JPH01110524U publication Critical patent/JPH01110524U/ja
Application granted granted Critical
Publication of JPH0638492Y2 publication Critical patent/JPH0638492Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案による一実施例の回路構成図、
第２図は入力インピーダンスの高いスイツチを複
数含んだ集積回路における本考案の他の実施例を
示す回路構成図である。第３図及び第４図は従来
の回路構成図、第５図は入力インピーダンスの高
いスイツチを複数含んだ集積回路の例を示す図で
ある。 Ａ：バツフア回路。 FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing another embodiment of the present invention in an integrated circuit including a plurality of switches with high input impedance. 3 and 4 are conventional circuit configuration diagrams, and FIG. 5 is a diagram showing an example of an integrated circuit including a plurality of switches with high input impedance. A: Buffer circuit.

Claims (1)

【実用新案登録請求の範囲】 １対のトランジスタのベースに入力されたバイ
アス電圧或いはアナログ入力信号のいずれを出力
させるかを切換えるアナログスイツチ回路におい
て、 バイアス電圧が入力されたトランジスタのベー
スとバイアス電圧印加端子間に、上記トランジス
タ対の一方のトランジスタに接続された回路と同
じ回路からなるバツフアを介挿してなることを特
徴とするアナログスイツチ回路。[Claims for Utility Model Registration] In an analog switch circuit that switches between outputting either a bias voltage input to the bases of a pair of transistors or an analog input signal, the base of the transistor to which the bias voltage is input and the bias voltage applied An analog switch circuit characterized in that a buffer consisting of the same circuit as the circuit connected to one transistor of the transistor pair is inserted between the terminals.
JP1988006386U 1988-01-21 1988-01-21 Analog switch circuit Expired - Lifetime JPH0638492Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988006386U JPH0638492Y2 (en) 1988-01-21 1988-01-21 Analog switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988006386U JPH0638492Y2 (en) 1988-01-21 1988-01-21 Analog switch circuit

Publications (2)

Publication Number Publication Date
JPH01110524U true JPH01110524U (en) 1989-07-26
JPH0638492Y2 JPH0638492Y2 (en) 1994-10-05

Family

ID=31210518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988006386U Expired - Lifetime JPH0638492Y2 (en) 1988-01-21 1988-01-21 Analog switch circuit

Country Status (1)

Country Link
JP (1) JPH0638492Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112723A (en) * 1982-12-20 1984-06-29 Hitachi Ltd Semiconductor circuit
JPS62266917A (en) * 1986-05-14 1987-11-19 Nec Corp Smiconductor logic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112723A (en) * 1982-12-20 1984-06-29 Hitachi Ltd Semiconductor circuit
JPS62266917A (en) * 1986-05-14 1987-11-19 Nec Corp Smiconductor logic circuit

Also Published As

Publication number Publication date
JPH0638492Y2 (en) 1994-10-05

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