JPH01746A - How to form wiring - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to the formation of wiring.

[Conventional technology]

The cross-sectional shape of wiring used in semiconductor devices is required to have a tapered or similar shape on the entire sidewall or a portion thereof in order to improve the coverage of the insulating layer.

A typical conventional method for forming interconnects with tapered sidewalls or a similar shape is a method that uses a combination of wet etching, in which etching progresses isotropically, and dry etching, in which etching is possible anisotropically. Figure 2 shows the outline.

First, as shown in FIG. 2(a), on a wafer substrate 201, an insulating layer 202, a conductive material layer 203, a photoresist) 8
204 is formed. Next, as shown in FIG. 2(b), the photoresist S 204 is patterned by exposure and development. Next, as shown in FIG. 2(C), conductive material 0
Wet etch layer 203 by a certain amount. Since wet etching progresses isotropically, the bottom of the edge portion of the patterned photoresist 2011 is etched into an arc shape. (In the figure, 205 indicates a part of the conductive material layer etched into a circular arch). Next, as shown in FIG. 2(d), the conductive material layer 203 is anisotropically etched by dry etching to form a wiring 206. Next, as shown in FIG. 2(e), the 7 photoresist 204 left on the wiring is removed.

After the above process, an arc-shaped part 205 is formed on the upper part of the side wall.
When forming an interlayer layer, a banoshi base film, etc. on a wiring layer, it is possible to improve the step coverage.

[Problem that the invention seeks to solve]

However, the wiring formed by the prior art described above has the following two problems.

First, since the arc-shaped portion of the side wall of the wiring is limited to the upper part of the wiring 1111 wall, improvement in step coverage of the living room insulation film, etc. is limited.

Second, because the conductive material under the patterned photoresist is partially etched and removed, the cross-sectional area is smaller than that of wiring formed by anisotropic etching, and electromigration etc. There is a risk of wire breakage. This second problem becomes more noticeable when the wet etching time is increased in order to avoid the first problem.

The present invention solves these problems, and its purpose is to increase the cross-sectional area (compared to that formed by anisotropic etching) and to add an arcuate portion to the side wall. It is an object of the present invention to provide a means for forming wiring provided with.

[Means for solving problems]

The wiring forming method according to the present invention includes, in the wiring forming process of a semiconductor device, a step of patterning and wiring a conductive material 0 layer by photoetching, and selectively growing a 4-conductor material around the patterned wiring. It is characterized by

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a diagram showing an example of the present invention in the order of steps, and shows an example in which tungsten (hereinafter referred to as W) is used as the wiring material and W is also used as the conductive material selectively grown around the wiring. The same applies to the four-electrode materials.

First, as shown in FIG. 1(a), an insulating layer lO
2. Form a conductive material layer 1o3 and a photoresist layer 104.

Next, as shown in FIG. 1(b), a portion of the conductive material layer 10'3 is removed by a photoetching process to form a wiring 105.

Next, as shown in Figure 1(C), WFg/H, gas 10
By CVD (chemical vapor deposition) using 6 as a lease gas, the reaction of WF, +3H,→W + 68 F is performed only on (surrounding) the wiring formed of W, and W atoms 107 are grown.

After the above steps, the wiring 105 is completed as shown in FIG. 1(d).
A new W atomic layer 108 can be formed around the .

Through the above steps, by newly forming a conductive material around the initially formed interconnect, it is possible to increase both the interconnect width and interconnect thickness of the interconnect initially formed in the photoetching process. Furthermore, since the W atomic layer is uniformly formed around the wiring, the upper part of the wiring sidewall has an r'ri arc shape. Therefore, by reducing the thickness of the wiring initially formed, substantially the entire wiring sidewall can be made into an arc shape.

In forming the wiring according to the present invention, the wiring material and the conductive material formed around it can be a combination of different species such as Sl, wlAL, and W. 2 W F s +33 i→2 W
After the Si surface is covered with W atoms by the reaction of +33 I Fa, it is possible to expand the W atomic layer around the Si by the method shown in FIGS. 2(a) to (d).

〔Effect of the invention〕

As described above, according to the manufacturing process according to the present invention, by newly forming a conductive material around the wiring once formed, it is possible to form an arc-shaped portion □ in the upper part of the wiring side wall. The arc-shaped portion can account for a portion of the force of the wiring sidewall by reducing the thickness of the wiring film initially formed.

Furthermore, as a result of forming a conductive material around the wiring, it becomes possible to increase the wiring width and the wiring film thickness.

As a result of the above, the method for forming wiring according to the present invention can obtain the following two advantages.

■ After wiring is formed, the coverage of the passivation film or living room insulation film is improved, making it possible to improve the reliability of the semiconductor device.

■ In the photo-etching process performed using the same level of microfabrication technology, it becomes possible to form interconnects with larger cross-sectional areas and narrower spacing, improving electromigration resistance and allowing finer interconnect design rules. is now possible.

[Brief explanation of the drawing]

1(a) to 1(d) are cross-sectional views of the manufacturing process of a wiring forming method according to an embodiment of the present invention. 101 is a cross-sectional view of a manufacturing process of a method for forming wafer 10 (on which semiconductor elements are formed).
2... Insulating layer 103... Conductive material cost 104... Photoresist 105... Wiring 106... Reactive gas (WF, /H,) 107... ~
V atoms 108... W atomic layer 201... Wafer 20 (on which semiconductor elements are formed)
2... Insulating layer 203... Conductive material layer 204... Photoresist 205... Portion 206 formed by isotropic etching
...Wiring and above Applicant Seiko Epson Co., Ltd. agent Patent attorney Tsutomu Mogami and 1 other person - ζ〉) i(j (often 1 Ce) Ren 2 causes

Claims (1)

[Claims] In the wiring formation process of a semiconductor device, a step of patterning a conductive material layer by photoetching to form wiring;
A method for forming a wiring, characterized in that a conductive material is selectively grown around the patterned wiring.