JPS64746A - Forming method of wiring - Google Patents

Forming method of wiring

Info

Publication number
JPS64746A
JPS64746A JP15569587A JP15569587A JPS64746A JP S64746 A JPS64746 A JP S64746A JP 15569587 A JP15569587 A JP 15569587A JP 15569587 A JP15569587 A JP 15569587A JP S64746 A JPS64746 A JP S64746A
Authority
JP
Japan
Prior art keywords
wirings
around
shaped
anew
sidewalls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15569587A
Other languages
Japanese (ja)
Other versions
JPH01746A (en
Inventor
Mikio Ota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP15569587A priority Critical patent/JPS64746A/en
Publication of JPH01746A publication Critical patent/JPH01746A/en
Publication of JPS64746A publication Critical patent/JPS64746A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To form arcuate sections to the upper sections of the sidewalls of wirings, to shape the wirings having larger sectional areas at narrower intervals, to improve electro-migration resistance and to fine the design rule of the wirings by anew forming conductive materials around the wirings shaped once.
CONSTITUTION: An insulating layer 102, a conductive material layer 103 and a photo-resist layer 104 are formed onto a wafer 101. One parts of the conductive material layer 103 are removed through a photoetching process, thus shaping wirings 105. W atoms 107 are grown only on the wirings formed by W through CVD using WF5/H2 gas 106 as a lease gas. W atomic layers 108 are shaped anew around the wirings 105 through said process. Accordingly, conductive materials are formed newly around the wirings shaped first, thus increasing both wiring width and wiring film thickness. The W atomic layers are formed uniformly around the wirings, thus shaping the upper sections of the sidewalls of the wirings to an arcuate shape.
COPYRIGHT: (C)1989,JPO&Japio
JP15569587A 1987-06-23 1987-06-23 Forming method of wiring Pending JPS64746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15569587A JPS64746A (en) 1987-06-23 1987-06-23 Forming method of wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15569587A JPS64746A (en) 1987-06-23 1987-06-23 Forming method of wiring

Publications (2)

Publication Number Publication Date
JPH01746A JPH01746A (en) 1989-01-05
JPS64746A true JPS64746A (en) 1989-01-05

Family

ID=15611512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15569587A Pending JPS64746A (en) 1987-06-23 1987-06-23 Forming method of wiring

Country Status (1)

Country Link
JP (1) JPS64746A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003051546A (en) * 2001-08-03 2003-02-21 Sony Corp Semiconductor device and semiconductor manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003051546A (en) * 2001-08-03 2003-02-21 Sony Corp Semiconductor device and semiconductor manufacturing method

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