JPH01757A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH01757A JPH01757A JP62-155681A JP15568187A JPH01757A JP H01757 A JPH01757 A JP H01757A JP 15568187 A JP15568187 A JP 15568187A JP H01757 A JPH01757 A JP H01757A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- region
- silicide
- layer
- design rules
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置特にＣＭＯ３からなるＬＳＩに有
効な半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, particularly a semiconductor device effective for an LSI made of CMO3.
本発明は、Ｐチャンネル領域とＮチャンネル領域の能動
領域には異なる膜厚のシリサイド層が裏打ちされること
を特徴とする。The present invention is characterized in that the active regions of the P-channel region and the N-channel region are lined with silicide layers having different thicknesses.
従来のシリサイド層を、Ｐ、Ｎ両領域に同じ膜厚のシリ
サイド層を形成していた。このため従来技術では、浅い
接合をＡｓ注入で形成できるＮチャンネル領域には、シ
リサイドの接合のつき抜けを避けるため薄いシリサイド
層のみしか形成できｆ、Ｐ、Ｎ両チャンネル領域が薄い
シリサイド層で形成される。In the conventional silicide layer, a silicide layer with the same thickness was formed in both the P and N regions. For this reason, in the conventional technology, only a thin silicide layer can be formed in the N channel region where a shallow junction can be formed by As implantation in order to avoid penetration of the silicide junction. be done.
このため、例えば、メモリ一部がＮチャンネルＭＯ３Ｆ
ＥＴ、周辺の回路がＰ１Ｎ両チャンネルＣＭ ＯＳ Ｆ
Ｅ ＴからなるスタティックＲＡＭなどにおいては、
スピードを律則するＰチャンネルトランジスタのゲイン
及び拡散層抵抗が、デザインルールで許される限界より
も、劣っているため、ＬＳＩの高速化を防げるという、
欠点を存していた。そして本発明はデザインルールの限
界内で最大限の電気特性を発揮でき、−層の高速化が達
成された半導体装置を提供することを目的とする。For this reason, for example, part of the memory is an N-channel MO3F
ET, peripheral circuit is P1N both channel CM OS F
In static RAM etc. consisting of ET,
It is said that the gain and diffusion layer resistance of the P-channel transistor, which governs speed, are lower than the limits allowed by design rules, which prevents the LSI from increasing in speed.
It had its shortcomings. It is an object of the present invention to provide a semiconductor device that can exhibit maximum electrical characteristics within the limits of design rules and achieves high-speed processing of -layers.
本発明は、かかる従来の欠点を解決するため、Ｐチャン
ネルの能動領域には、デザインルールで許される、 す
なわちＰチャンネルＭ ＯＳ Ｆ Ｅ Ｔの電気特性で
制限される集密限度のシリサイド層を、Ｎチャンネル領
域のシリサイド層より厚く形成している。本発明によれ
ばＰ％Ｎ両チケチヤンネル領域いて、シリサイド層の膜
厚を独立に最適化するためＮＰＳＮ両チャンネルＭＯ５
ＦＥＴがデザインルールの限界内で最大限の電気特性、
（ゲイン、種々の抵抗など）を発揮でき、ＬＳＩの高速
化を可能にする。In order to solve such conventional drawbacks, the present invention includes a silicide layer in the active region of the P-channel with a density limit allowed by the design rules, that is, limited by the electrical characteristics of the P-channel MOSFET. It is formed thicker than the silicide layer in the N channel region. According to the present invention, there is a P%N double channel channel region, and the NPSN double channel MO5 is used to independently optimize the film thickness of the silicide layer.
FETs with maximum electrical characteristics within the limits of design rules,
(gain, various resistances, etc.), making it possible to increase the speed of LSI.
以下Ｔｉシリサイドを用いて実施例を示す。Ｔｉは、Ｓ
ｉとの反応によりＴｉ５ｉｔを形成するが、反応熱処理
を適当に選べば、Ｔ ｉ Ｓ １ ｔの形成はＳｉ中の
不純物ｊｆＡ度に依存することが明らかになった。例え
ば、Ｉ３Ｆ、イオン注入シリコンとＡｓイオンを５Ｘ１
０” ｃｍ−’注入したシリコン上にＴｉを６００人
形成後、６８０°Ｃ〜７００℃で３０ｓアニールするこ
とにより、ＢＦ、イオン注入層上には約０．１μｍのＴ
ｉ Ｓ Ｉ ＊が形成され、ＡＳ注入領域上には約０
．０６μｍのＴｉＳ ｌｚとＴｉＳｉが形成される。１
ＴＩＳｉは、ＲＣＡ液により除去されるため、同一のプ
ロセスでＰチャンネルとＮチャンネル領域に異なる膜厚
のＴｉシリサイドが形成される。一般に、Ｎチャンネル
ｈ、１０５ Ｆ Ｅ Ｔからなるメモリ一部ではデザイ
ンルールが厳しいため、接合も浅くなりＴｉシリサイド
も厚くない。一方、周辺回路部でデザインルールがメモ
リ一部に比べて厳しくな（、ＰチャンネルＭ ＯＳ Ｆ
Ｅ Ｔについては、微細化よりも電気特性の向上が要
求される。Examples will be shown below using Ti silicide. Ti is S
Ti5it is formed by reaction with Si, but it has become clear that if the reaction heat treatment is appropriately selected, the formation of TiS1t depends on the degree of impurity jfA in Si. For example, I3F, ion-implanted silicon and As ions are combined 5X1.
After forming 600 layers of Ti on the implanted silicon and annealing for 30 seconds at 680°C to 700°C, a T layer of about 0.1 μm was deposited on the BF and ion-implanted layers.
i S I * is formed, and about 0 on the AS implanted region
．． 06 μm of TiS lz and TiSi are formed. 1
Since TISi is removed by the RCA solution, Ti silicide with different thicknesses is formed in the P-channel and N-channel regions in the same process. Generally, design rules are strict for a part of a memory consisting of an N-channel h, 105 FET, so the junction is shallow and the Ti silicide is not thick. On the other hand, the design rules for the peripheral circuit section are stricter than for the memory section (P-channel MOS F
Regarding ET, improvement in electrical properties is required rather than miniaturization.
本発明によれば、ＴｉとＳｉとの反応温度及びＰ、Ｎチ
ャンネル、特にＡｓまたはＰの注入量を約１０” 〜１
０” ｃｍ−’の範囲で最適化することにより、Ｎチャ
ンネル領域のシリサイド層は薄く、かつ、Ｐチャンネル
領域のシリサイド層はデザイン・ルールの許容範囲内で
厚くすることが出来、Ｐチャンネルトランジスタのゲイ
ンを大きく、シート抵抗、配線とのコンタクト抵抗の低
減を可能にする。According to the present invention, the reaction temperature of Ti and Si and the injection amount of P, N channels, especially As or P, are adjusted to about 10" to 1
By optimizing in the range of 0"cm-', the silicide layer in the N-channel region can be made thin and the silicide layer in the P-channel region can be made thick within the allowable range of design rules. Enables large gain, reduction of sheet resistance and contact resistance with wiring.
第１図は、本発明によるＣ Ｍ Ｓ Ｆ Ｅ Ｔの構造
断面積を示す図。Ｐｃｈ領域のＴ Ｉ Ｓ ｓ ｔ ９
はＮｃｈ ｔｆｊＩ域のＴｉＳｉ、８よりも厚いことを
示す。
１・・・Ｓｉ基板 ２・・・絶縁膜 ３・・・ゲート膜
４・・・サイドワール絶縁物 ５・・・Ｎｃｈ拡散層
６・・・Ｐｃｈ拡散層 ７・・・ゲート電極８・・・Ｎ
ｃｈ領域Ｔ ｉＳ ｓ を層９−Ｐ ｃ ｈ領域Ｔｉ５
ｉｔ層
以 上
出願人 セイコーエプソン株式会社FIG. 1 is a diagram showing a structural cross-sectional area of a CMS FET according to the present invention. T I S t 9 of Pch region
indicates that it is thicker than TiSi, 8 in the Nch tfjI region. DESCRIPTION OF SYMBOLS 1...Si substrate 2...Insulating film 3...Gate film 4...Sidewar insulator 5...Nch diffusion layer 6...Pch diffusion layer 7...Gate electrode 8... N
ch region T iS s layer 9-P ch h region Ti5
Applicant for IT layer and above Seiko Epson Corporation
Claims (1)
ンネル領域の能動領域には、Ｎチャンネル領域の能動領
域よりも、より厚いシリサイド膜が裏打ちされてなるこ
とを特徴とする半導体装置。1. A semiconductor device comprising a CMOSFET, wherein an active region of a P-channel region is lined with a thicker silicide film than an active region of an N-channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62155681A JP2658057B2 (en) | 1987-06-23 | 1987-06-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62155681A JP2658057B2 (en) | 1987-06-23 | 1987-06-23 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH01757A true JPH01757A (en) | 1989-01-05 |
| JPS64757A JPS64757A (en) | 1989-01-05 |
| JP2658057B2 JP2658057B2 (en) | 1997-09-30 |
Family
ID=15611242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62155681A Expired - Lifetime JP2658057B2 (en) | 1987-06-23 | 1987-06-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2658057B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3514500B2 (en) | 1994-01-28 | 2004-03-31 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
| JP2005057301A (en) * | 2000-12-08 | 2005-03-03 | Renesas Technology Corp | Semiconductor device and method of manufacturing same |
| JP2003086708A (en) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6295822A (en) * | 1985-10-23 | 1987-05-02 | Hitachi Ltd | Manufacturing method of semiconductor device |
-
1987
- 1987-06-23 JP JP62155681A patent/JP2658057B2/en not_active Expired - Lifetime
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