JPH0176643U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a case in which an embodiment of the present invention is applied facing each other; FIG. 2 is a timing diagram showing an example of the sending timing of the request signal, confirmation signal, and data in FIG. Fig. 3 is a block diagram showing an example of use when conventional interface devices are used facing each other, and Fig. 4 shows the transmission of request signals, confirmation signals, and data in the conventional interface devices shown in Fig. 3. FIG. 3 is a timing chart showing an example of timing. 1, 2...Interface device, 3...Request signal line, 3a, 3b...Signal generation circuit, 4...Confirmation signal line,
4a, 4b...Signal receiving circuit, 5...Data line, 6a
, 6b...Data processing circuit, 7a, 7b...Buffer, 8a, 8b...Timer circuit, 9a, 9b...Timer setting circuit, 11, 12...Conventional interface device, 13...Request signal line, 13a, 13b...Signal generation Circuit, 14... Confirmation signal line, 14a, 14b... Signal receiving circuit, 15... Data line, 16a, 16b...
Data processing circuit, 17a, 17b... buffer.

Claims (1)

[Scope of utility model registration request] In an interface device having a sending circuit that sends out a request signal for requesting permission to transfer information, and a receiving circuit that receives a confirmation signal in response to the request signal, the transfer of the information is terminated after receiving the confirmation signal. An interface device comprising a timing signal generation circuit that generates and transmits a preset timing signal.