JPH0187458U - - Google Patents

Info

Publication number
JPH0187458U
JPH0187458U JP18108387U JP18108387U JPH0187458U JP H0187458 U JPH0187458 U JP H0187458U JP 18108387 U JP18108387 U JP 18108387U JP 18108387 U JP18108387 U JP 18108387U JP H0187458 U JPH0187458 U JP H0187458U
Authority
JP
Japan
Prior art keywords
transmitting
receiving
data
cpu
bus line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18108387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18108387U priority Critical patent/JPH0187458U/ja
Publication of JPH0187458U publication Critical patent/JPH0187458U/ja
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すハードウエア
構成図、第2図は同上実施例の送・受信方式のフ
ローチヤート、第3図は同上実施例のタイミング
チヤート、第4図は従来例を示すハードウエア構
成図、第5図は従来例の送・受信方式のフローチ
ヤート、第6図は従来例のタイミングチヤートで
ある。 1……マスターCPU、2……スレーブCPU
、3……双方向バスライン、4……抵抗。
Fig. 1 is a hardware configuration diagram showing an embodiment of the present invention, Fig. 2 is a flowchart of the transmission/reception system of the above embodiment, Fig. 3 is a timing chart of the above embodiment, and Fig. 4 is a conventional example. 5 is a flowchart of a conventional transmission/reception system, and FIG. 6 is a timing chart of a conventional example. 1...Master CPU, 2...Slave CPU
, 3...bidirectional bus line, 4...resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のCPU間を双方向バスラインにより接続
して、相互にデータの送信及び受信を行うCPU
間データ送受信装置において、前記双方向バスラ
インに抵抗を挿入すると共に、送信と受信のタイ
ミングを一部オーバーラツプさせつつデータの送
信及び受信を行うデータ送受信制御手段を設けた
ことを特徴とするCPU間データ送受信装置。
A CPU that connects multiple CPUs with a bidirectional bus line to mutually send and receive data.
The CPU-to-CPU data transmitting/receiving device is characterized in that a resistor is inserted into the bidirectional bus line, and data transmitting/receiving control means is provided for transmitting and receiving data while partially overlapping the timings of transmitting and receiving. Data transmitting/receiving device.
JP18108387U 1987-11-30 1987-11-30 Pending JPH0187458U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18108387U JPH0187458U (en) 1987-11-30 1987-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18108387U JPH0187458U (en) 1987-11-30 1987-11-30

Publications (1)

Publication Number Publication Date
JPH0187458U true JPH0187458U (en) 1989-06-09

Family

ID=31472581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18108387U Pending JPH0187458U (en) 1987-11-30 1987-11-30

Country Status (1)

Country Link
JP (1) JPH0187458U (en)

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