JPH01781A - Semiconductor-coupled superconducting circuit device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor-coupled superconducting circuit device and a method for manufacturing the same, and particularly to the structure of a semiconductor-coupled portion of a superconducting electrode of a semiconductor-coupled superconducting circuit device and its manufacturing method. Regarding the manufacturing method.

[Prior art and problems to be solved by the invention] In order to apply superconducting elements to integrated circuits (ICs), it is necessary to develop a three-terminal structure that provides excellent current control characteristics. As such a three-terminal superconducting element, a semiconductor-coupled superconducting transistor has been proposed in which the superconducting current is controlled by the Ga)%E pressure.

This gate-controlled superconducting transistor uses superconducting electrons (Cooper pairs) that seep into the semiconductor from two superconducting electrodes used as drain electrodes.
air) by controlling the degree of overlap of the wave functions of the source using the gate voltage.

This element controls the superconducting current flowing between the drains.

The amplitude of the wave function of superconducting electrons penetrating into the semiconductor (order parameter)
) is a predetermined value (for example, 1/e), the spatial distance required is the coherence length (coherence long
h). The longer the coherence length, the greater the degree of overlap of the wave functions of superconducting electrons, and the greater the superconducting current. What is coherence length ξ and carrier concentration n?
Since it has the relationship Oe H"', the coherence length of superconducting electrons can be changed by changing the gate voltage and changing the carrier concentration. In this way, changing the gate voltage The superconducting current flowing between the source and drain is controlled by

An example of a conventional semiconductor-coupled superconducting circuit device is the magazine ``IEEE Electron Device Letter (IEEE Electron Device Letter)''.
ceLetters) JED L-Volume 6, June 19
There is one mentioned on page 85,297. As shown in FIG. 10, in this conventional example, a gate electrode 101 is provided on a side of a silicon substrate 103 opposite to a superconducting electrode 104 side with a gate insulating film 102 in between.

In such a structure, in order to effectively influence the coherence length of superconducting electrons seeping into the silicon substrate 103 from the superconducting electrode 104 by changing the gate voltage and changing the carrier concentration of the silicon substrate 103, it is necessary to , the thickness of the silicon substrate 103 on the gate electrode 101 is about 1100 nm, and in order to make the operating characteristics of the conduction transistor uniform, the silicon substrate 103 and the gate insulating film 102 are
It was necessary to make the film thickness uniform. However, in this way, the extremely thin silicon substrate 103 and gate insulating film 1
It was extremely difficult to form 02 within an IC chip with good uniformity in film thickness and film quality, and without defects such as pinholes. Furthermore, such a very thin region has weak mechanical strength and low reliability. Further, the superconducting electrodes 104 are formed by an ion etching method using Ar, but according to this method, the crystallinity of the surface of the silicon substrate 103 exposed between the superconducting electrodes 104 is reduced by a sputtering phenomenon caused by ions, It has the disadvantage that it deteriorates due to embedding of ions and sputtered materials, resulting in deterioration of conduction characteristics.

Further, as other examples of conventional semiconductor-coupled superconducting circuit devices, for example, "IDEM"
85 Proceedings J4-698.

In this conventional example, as shown in FIG.
A gate electrode 114 was provided between the superconducting electrodes 112 embedded in one surface with a gate oxide film 113 interposed therebetween. Since this device controls the surface potential of the surface inversion layer of the semiconductor substrate 111 with high sensitivity using the gate voltage, the thickness of the gate oxide film 113 is made as thin as about 1100 nm.
It was necessary to use a high-quality gate oxide film. And I
In order to make the operating characteristics of the superconducting transistor uniform within the C chip, it was necessary to make the thickness of the gate oxide film 113 uniform. However, it is difficult to form such a very thin gate oxide film 113 on the semiconductor substrate 111 and superconducting electrode 112 in an IC chip with good uniformity in film thickness and film quality, and without defects such as pinholes. This was extremely difficult because the thermal oxidation technique used for silicon and the like was not used. Furthermore, although SiO is used as the gate oxide film 113 in this conventional example, since SiO is an unstable compound, there is a risk of causing variations in device characteristics.

[Means to solve the problem]

The purpose of the present invention is to eliminate the need to provide a thin semiconductor layer or insulating film under the gate electrode, provide uniform device characteristics, and achieve high yield.
An object of the present invention is to provide a semiconductor-coupled superconducting circuit device that enables high integration.

Furthermore, another object of the present invention is to provide a method for manufacturing a semiconductor-coupled superconducting circuit device without degrading the crystallinity of the surface of a semiconductor substrate exposed between superconducting electrodes.

According to the present invention, the first semiconductor layer of one conductivity type;
A second semiconductor layer of another conductivity type provided on the first semiconductor layer, and first and second superconducting layers provided in contact with the surface of the second semiconductor layer and spaced apart from each other. A semiconductor-coupled superconducting circuit device having electrodes is obtained.

Further, according to the present invention, there is a step of forming a lift-off die in contact with the main surface of the first semiconductor layer of one conductivity type, and using the die as a doping mask to form a lift-off die in the first semiconductor layer. forming a second semiconductor layer of another conductivity type;
After depositing a superconductor film on the second semiconductor layer and the cutting die, the superconductor film is patterned using the lift-off method using the cutting die, thereby depositing the superconductor on the second semiconductor layer. Semiconductor-coupled superconductor comprising a step of selectively providing a third semiconductor layer of another conductivity type under the surface of the first semiconductor layer exposed by removing the superconductor film. A method for manufacturing a circuit device is obtained.

[Effect]

In the semiconductor-coupled superconducting circuit device of the present invention, superconducting electrons seep out from the first and second superconducting electrodes to the surface of the second semiconductor layer. The coherence length (ξ) of the superconducting electrons seeping into the second semiconductor layer has a relationship of ξQCN 1 to the carrier concentration (N) below the main surface in the semiconductor layer. Therefore, by changing the carrier concentration N near the surface in the second semiconductor layer, the coherence length ξ changes, and the magnitude of the superconducting current, which depends on the amount of overlap of wave functions between superconducting electron pairs, is controlled. I can do that.

In the present invention, the carrier concentration generated between the pn junctions is changed by changing the reverse bias voltage between the pn junctions generated between the first semiconductor layer of one conductivity type and the second semiconductor layer of the other conductivity type. The width (W) of the depletion layer where N=0 is changed. This depletion layer extends from the PN junction surface toward the surface of the second semiconductor layer as the reverse bias voltage applied between the PN junctions increases, so that the carrier concentration N in the second semiconductor layer decreases and becomes superfluous. The coherence length of the conduction electron pair becomes shorter, and the overlap of the wave functions of the superconducting electron pair becomes smaller. In this way, by controlling the reverse bias voltage applied to the first and second semiconductor layers, the superconducting current flowing between the two superconducting electrodes can be controlled.

In this way, the semiconductor-coupled superconducting circuit device of the present invention
Since the superconducting current is controlled by the width of the depletion layer generated in the PN junction, it can be easily formed by forming a PN junction on the surface of a semiconductor substrate with a normal thickness. Therefore, there is no need to provide an extremely thin semiconductor layer or insulating film, and device characteristics are uniform, allowing high yield and high integration.

In addition, since the method for manufacturing a semiconductor-coupled superconducting circuit device of the present invention uses a lift-off die to form superconducting electrodes, when forming superconducting electrodes, the semiconductor layer exposed between these electrodes is The crystallinity of the surface is not impaired, and therefore the characteristics of the superconducting element are not deteriorated.

〔Example〕

FIG. 1 is an m1 plane view of a semiconductor-coupled superconducting circuit device according to a first embodiment of the present invention. 5 on the n-type silicon substrate 11
A P empty region 12 in which poron (B) of X 10 ” atoms/ail is implanted is formed. The first superconducting electrode 13 and the second superconducting electrode 14 each have a thickness of 300 mm.
A niobium film of nanometer diameter is used.

1st. The distance between the second superconducting electrodes (13-14) is 2
00 nm, and the thickness of the p-type region 12 directly under the electrode gap is 200 nm. These first. Between the second superconducting electrodes (
13-14), the superconducting current flowing through the n-type substrate 11 and the p-
It is controlled by a reverse voltage applied between the relevant regions 12.

FIG. 2 is a sectional view showing a second embodiment of the invention. 5 x 1020 atoms/cnf on an n-type silicon substrate 21 containing phosphorus at 3 x 10” atoms/cl
P+ region 22 and 5, x 10'' implanted with poron of
A P- region 23 implanted with atoms/ad poron is formed. The first superconducting electrode 24 and the second superconducting electrode 25 each use a niobium film with a thickness of 300 nm,
It is provided on the surface of the P+ region 22. 1st. The distance between the second superconducting electrodes is 200 nm and the P+ region 22.
P-region 23. The thickness is 200 nm.

As described above, the carrier concentration n of the semiconductor layer below the superconducting electrode and the coherence length ξ of superconducting electrons (Cooper pairs) have a relationship of ξOe n''.

That is, the higher the carrier concentration, the longer the coherence becomes, and the distance between the two superconducting electrodes can be increased. Therefore, by increasing the carrier concentration of the semiconductor layer, the superconducting electrode can be easily bonded, and the superconducting current can also be increased. The superconducting current flowing between two superconducting electrodes is controlled by the width of the depletion layer extending from the pn junction surface toward the surface, and the width of this depletion layer has the property of increasing in inverse proportion to the carrier concentration. There is. Therefore, if the semiconductor layer under the superconducting electrodes is uniformly made highly concentrated, the distance between the superconducting electrodes can be kept relatively large, but the amount of change in the superconducting current with respect to the reverse bias voltage applied to the pn junction is It becomes smaller.

In this embodiment, since the semiconductor layer under the superconducting electrodes 24.25 is the highly concentrated P+ region 22, the coherence length of the superconducting electrons seeping into the semiconductor layer 22 from each superconducting electrode 24.25 becomes long. , the distance between the two electrodes can be relatively large, and the superconducting current can also be large. Furthermore, since the semiconductor layer between the superconducting electrodes 24 and 25 is a low concentration P- region 23, the depletion layer can be easily extended toward the surface from the PN junction surface, and the superconducting current between the superconducting electrodes can be Can be easily controlled.

Therefore, by making the semiconductor layer under the superconducting electrodes have a high concentration and the semiconductor layer between the superconducting electrodes having a low concentration as in this example, the distance between the superconducting electrodes can be increased, and the distance between these electrodes can be increased. It is possible to increase the superconducting current flowing in the p
The amount of change in superconducting current with respect to the reverse bias voltage applied to the n-junction can be increased.

FIG. 3 is a sectional view showing a third embodiment of the present invention, and FIG. 4 is a perspective view. Phosphorus 3X1017 atoms
5 on the n-type silicon (111) substrate 31 containing /crA.
P+ region 32 injected with poron of X 10 ”atoms/cuff and 5 X 10 ”atoms/an! A P- region 33 in which poron is implanted is formed. 1st
A superconducting electrode 34 and a second superconducting electrode 35 are each provided on the main surface of the P+ region 32 using a niobium film with a thickness of 300 nm. 1st. The distance between the second superconducting electrodes is 200 nm, and the thickness of the P+ region 32 is 200 nm.
, the thickness of the P- region 33 is 1100n. Also, the fourth
As shown in the figure, the n-type silicon substrate 31 is connected to the VBO terminal, the first superconducting electrode 34 is connected to the vs terminal, and the second superconducting electrode 35 is connected to Vn.

If the depth of the highly concentrated P+ region 32 under the superconducting electrode 34.35 is increased, the wave function of superconducting electrons seeping into the semiconductor layer under the superconducting electrode 34.35 can be changed by the carrier concentration of the semiconductor layer. It can be extended to a fixed coherence length. Therefore, it is desirable that the thickness of the highly concentrated semiconductor layer 32 under the superconducting electrodes 34, 35 be increased to the coherence length. Note that even if the thickness is increased further, the wave function of superconducting electrons will not extend beyond the coherence length.

The amplitude (order parameter) of the wave function of the superconductor seeping out of the superconducting electrodes 34, 35 is greatest at the interface between the superconducting electrode and the semiconductor layer, and decreases as it moves away from this interface. Therefore, also in the semiconductor layer 33 between the two superconducting electrodes 34 and 35, the order parameter of the wave function of superconducting electrons is largest at the surface and becomes smaller as it gets deeper. In other words, the superconducting current flowing on the surface is the largest and decreases as the surface becomes cleaner. Therefore, in order to increase and efficiently control the amount of change in the superconducting current with respect to the reverse bias voltage applied to the pn junction, it is necessary to reduce the thickness of the semiconductor layer between the superconducting electrodes and form the pn junction surface shallowly. . By doing so, the depletion layer can easily reach the surface, and the controllability of the superconducting current can be improved. Furthermore, by lowering the concentration of the semiconductor layer 33 between the superconducting electrodes 34 and 35, the controllability of the superconducting current can be improved.

The depth of the high concentration P1 region 32 under the present superconducting electrodes 34 and 35 is set to 200n, which is approximately equal to the coherence length of superconducting electrons.
Since it is set to m, the wave function of superconducting electrons seeping out from the superconducting electrodes 34 and 35 can be sufficiently extended,
The distance between the superconducting electrodes 34 and 35 can be increased, and the superconducting current can also be increased. Furthermore, since the semiconductor layer 33 between the superconducting electrodes 34 and 35 is made as thin as 1100 nm, the amount of change in superconducting current with respect to the reverse bias voltage applied to the pn junction can be increased. Furthermore, since the semiconductor layer 33 is a low concentration P- region, the superconducting current can be controlled more efficiently.

FIG. 5 shows the current-voltage characteristics between the superconducting electrodes 34 and 35 at 4.2 K of the semiconductor-coupled superconducting circuit device shown in FIGS. 3 and 4. The sizes of the superconducting electrodes are L=1.0 μm and W=3.0 μm in FIG. 4, respectively.
It is 0 μm. Here, l vol was changed to a reverse bias voltage l VBa Vs l to 11 mV applied between the n-type silicon substrate 31 and the P- region 33. By applying a reverse bias voltage, the superconducting electrode 34
．． The superconducting current flowing between 35 and 35 is decreasing. Moreover, the switching speed was about 10 picoseconds.

Figures 6(a) to 6(d) represent the third
3 shows the main steps of the method for manufacturing the semiconductor-coupled superconducting circuit device according to the embodiment.

First, as shown in Figure 6(a), 3×1017 phosphorus
On the surface of the n-type substrate 41 containing atoms/ad, polymethyl methacrylate (po
ly-methyl-meta acrylate:P
MMA) is applied to a thickness of 1 μm. Next, the acceleration voltage 20
K.V.

Exposure was performed directly with an electron beam without using a mask at a dose of 2XIO-'coulombs/d. Thereafter, by performing development, a lift-off cutting die 36 having a width of 0.2 μm is formed on the surface of the pn type substrate 31.

Next, as shown in FIG. 6(b), poron (B) was doped by ion implantation to give a surface concentration of 5×10”a.
A P+ region 32 is formed at a depth of 200 nm.

Thereafter, as shown in FIG. 6(C), a niobium film is deposited to a thickness of 300 nm by sputtering, and then lift-off is performed in acetone to pattern the niobium film, forming the first superconducting electrode 34. ．． A second superconducting electrode 35 is formed.

Thereafter, as shown in FIG. 6(d), poron was implanted at a surface concentration of 5×10”atoms/at by ion implantation.
The P- region 33 is formed by implanting to a depth of 1100n.

When ions are implanted into a superconductor, crystal defects and damage occur, which lowers the critical temperature. Therefore, superconducting electrode 3
The thickness of 4.35 mm is preferably greater than the thickness of the damaged layer formed by ion implantation. By increasing the thickness in this way, the interface characteristics between the superconducting electrodes 34, 35 and the P+ semiconductor layer 32 are also kept good, and the coherence length of superconducting electrons does not become short.

As described above, in the semiconductor layer between the superconducting electrodes 34 and 35, the superconducting current is largest at the surface and becomes smaller as the depth increases. For this purpose, superconducting electrode 34.3'5
When forming the superconducting electrodes 34 and 35, a method is desired that causes as little damage as possible to the surface of the semiconductor layer exposed between the superconducting electrodes 34 and 35. Therefore, superconducting electrodes can be subjected to RIE (
It cannot be said that it is a preferable method to process the material by a method such as reactive ton eeching. This is because the components of the superconducting electrode are buried in the back surface of the semiconductor layer by the ions, deteriorating the conduction characteristics.

If a superconducting electrode is formed by the lift-off method using a resist as in this example, the surface of the semiconductor layer will not be damaged during lift-off, and this is an excellent method for forming a semiconductor-coupled superconducting circuit device. It is something that

Furthermore, the superconducting electrode and the channel region can be simultaneously determined in self-alignment through the second pattern transfer process. As a result, the precision of microfabrication of the device can be improved, and the manufacturing process can be simplified.

Next, a fourth embodiment using an oxide superconductor for the superconducting electrode will be described using FIGS. 7(a) to 7(d).

First, as shown in FIG. 7(a), 5×10” at
A lift-off cutting die 7 with a width of 0.1 μm is formed using a photoresist on the surface of an n-type substrate 71 containing phosphorus of oms/d.
form 6.

Next, as shown in FIG. 7(b), poron was doped by ion implantation to a surface concentration of 5×1020 atoms.
/c% A P+ region 72 is formed to a depth of 200 um.

Next, as shown in FIG. 7(c), the pressure is 4X10-'P
Yttrium, barium oxide, and copper were sequentially deposited using an electron gun at a deposition rate of 1 nm/min under a vacuum of
A μm thick YIBa, Cu5or film is deposited. Next, oxygen I
Argon laser was irradiated in an atmosphere of Pa. The conditions for argon laser irradiation were an output IW, a beam diameter of 40 μm, and a scanning speed of 20 nm/sec. As a result, oxygen injection and sintering proceeded simultaneously, and a superconducting electrode 74 made of Y, Ba 2 Cu 30 & e oxide superconductor was formed. 75 was formed. The oxide superconductor film deposited on the upper part of the resist portion 76 was lifted off at the same time as the resist 76 was removed by argon laser irradiation in an oxygen atmosphere. Thereafter, as shown in FIG. 7(d), poron was implanted at a surface concentration of 5 x 10'' atoms/cd and a depth of 10 nm by ion implantation.
A P- region 73 was formed. .

FIG. 8 shows the current-voltage characteristics at 80K of the semiconductor-coupled superconducting circuit device using the oxide superconductor thus formed.

The size of the superconducting electrodes 74 and 75 is 1 .mu.m.times.3 .mu.m, which is the same as the element of the third embodiment shown in FIG.

In this example, the fifth
Characteristics similar to those of the third embodiment shown in the figure are obtained. Matk
The time interval was approximately 10 picoseconds.

Although silicon was used as the semiconductor substrate in the above embodiments, germanium could also be used, InAs,
It is also possible to use compound semiconductors such as InSb, GaAs, and InP.

A fifth embodiment using, for example, GaAs will be explained in the order of manufacturing steps with reference to FIGS. 9(a) to 9(d).

First, as shown in FIG. 9(a), 5×1017at
n-type (100) Ga containing Si at oms/d concentration
A 200 nm wide cutting die 96 for lift-off is formed on the surface of the As substrate 91 using photoresist.

Next, as shown in FIG. 9(b), Mg is doped by an ion implantation method accelerated at 120 KeV, and the surface concentration is 3 x
10 atoms/ant, P” at a depth of 200 nm
A region 92 is formed.

Next, as shown in FIG. 9(c), after depositing a Nb film with a thickness of 300 nm by sputtering, the resist is removed in acetone or by a lift-off method. A second superconducting electrode 94,95 is formed.

Thereafter, as shown in FIG. 9(d), Mg is implanted by ion implantation to a depth of 1100n at a surface concentration of 3.times.10" atoms/crA to form a P- region 93.

The coherence length ξ and mobility μ of superconducting electrons are ξ (branch)
Since there is a relationship of .mu.m/2, if a compound semiconductor with high mobility is used as in this embodiment, the distance between the superconducting electrodes can be increased, manufacturing is easy, and a large superconducting current can be obtained.

Note that similar effects can be obtained even if the conductivity types of the semiconductor layers in the above embodiments are reversed.

Furthermore, pb, Nb, and Si are used as superconducting electrodes.

Superconducting metals such as Nb3Sn, NbN, NbCxN+-x, MoN, B a-P b -B i-0 system, La-
Ba-Cu-0 series, La-8r-Cu-0 series, La-C
a-Cu-0 series, Y-Ba-Cu70 series, B1-8r-
Ca-Cu-0-based oxide superconductors and superconductors obtained by adding A4 or F to these oxide superconductors can be used. Even when these superconductors are used, the manufacturing method shown in the above-mentioned embodiments can be applied. Also, the substrate 11.21
．． The concentration of 31.71.91 is 1014 atoms/c
It is preferable that the impurity concentration of the high concentration semiconductor layer 22, 32°72.92 is 10 atoms/all to 10” atoms/cl.
/ant, and the low concentration semiconductor layer 23.
The concentration of 33,73.93 is 1014 atoms/cn
t~10'' atoms/cnff is preferable, and it is preferable that the concentrations of these high concentration semiconductor layers 22, 32, 72.92 and low concentration semiconductor layers 23, 33, 73.93 are different by one order of magnitude or more. ..

Note that the depth of the high concentration semiconductor layers 22, 32, 72, and 92 is preferably 1100 nm to 400 nm, and the depth of the low concentration semiconductor layer 3 is preferably 1100 nm to 400 nm.
The depth of 3, 73, and 93 is selected to be 10 nm to 200 nm.

The distance between the superconducting electrodes 34, 35 near 4, 75: 94, 95 is less than twice the coherence length of the superconducting electron pair, and 1
The thickness is preferably 0 nm to 400 nm. [Effects of the Invention] As explained above, the present invention provides a first semiconductor layer of one conductivity type and a second semiconductor layer of another conductivity type. 2
Two superconductor electrodes are provided on the semiconductor layer, and the superconducting current flowing between the superconductor electrodes is controlled by changing the width of the depletion layer created in the PN junction, so it is not possible to use a conventional extremely thin substrate. It is possible to use a substrate with relaxed thickness restrictions, and it is also possible to realize a semiconductor-coupled superconducting circuit device that does not require an extremely thin insulating layer.
Uniform element characteristics can be easily achieved, yields can be increased, and a device suitable for high integration can be realized.

Furthermore, by making the second semiconductor layer under the two superconducting electrodes have a high impurity concentration, the distance between the superconducting electrodes can be increased, and the superconducting current can also be increased.

The ability to increase the distance between the superconducting electrodes in this way has a particularly excellent effect when using an oxide superconductor in which the coherence length of superconducting electrons is short. Furthermore, by making the second semiconductor layer between the superconducting electrodes have a low impurity concentration, the amount of change in the superconducting current with respect to the gate voltage can be increased and controllability can be increased.

Further, by deepening the second semiconductor layer under the superconducting electrodes, the distance between the superconducting electrodes can be increased, and the superconducting current can also be increased. In this case as well, since the distance between the superconducting electrodes can be made large, particularly excellent effects can be obtained when an oxide superconductor in which the coherence length of superconducting electrons is short is used. Furthermore, by forming the second semiconductor layer between the superconducting electrodes shallowly, the PN junction surface can be formed shallowly, and the controllability over the gate voltage can be increased.

Since the manufacturing method of the present invention forms the superconducting electrodes by a lift-off method, the crystallinity of the surface of the semiconductor layer exposed between the superconducting electrodes is not impaired, and the device characteristics are not deteriorated. In addition, according to the manufacturing method of the present invention, a semiconductor-coupled superconductor in which a p-n junction is formed in a substrate whose thickness is more relaxed than before, or a semiconductor substrate that does not require an extremely thin insulating layer. Since a circuit device can be realized, device characteristics can be made uniform, yields can be increased, and a device suitable for high integration can be realized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor-coupled superconducting circuit device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor-coupled superconducting circuit device according to a second embodiment of the present invention, and FIG. The figure is a sectional view of a semiconductor-coupled superconducting circuit device according to a third embodiment of the present invention, FIG. 4 is a perspective view of a semiconductor-coupled superconducting circuit device according to a third embodiment of the present invention, and FIG. A current-voltage characteristic diagram of a semiconductor-coupled superconducting circuit device according to a third embodiment of the present invention, FIG.
) to (d) are cross-sectional views for explaining the manufacturing method of a semiconductor-coupled superconducting circuit device according to the third embodiment of the present invention, and FIGS. A sectional view showing the order of the main manufacturing steps for explaining the semiconductor-coupled superconducting circuit device of the embodiment, and FIG. 8 shows the current-voltage characteristics of the semiconductor-coupled superconducting circuit device of the fourth embodiment of the present invention. - Figures 9 and 9 are cross-sectional views shown in the order of main manufacturing steps for explaining the semiconductor-coupled superconducting circuit device of the fifth embodiment of the present invention, and Figure 10.
FIG. 11 is a sectional view of a conventional semiconductor-coupled superconducting circuit device. 11...N-type substrate, 12...P-type region, 13...First superconducting electrode, 14...
・Second superconducting electrode, 21...n-type substrate, 22
...P+ area, 23...P- region, 2
4...First superconducting electrode, 25... Second superconducting electrode, 31... N-type substrate, 32'-
・Song・P+ area, 33...P- area, 34...
...First superconducting electrode, 35... Second superconducting electrode, 36... Lift-off cutting die, 71.
...N-type substrate, 72. Old...P+ type region, 73.
...P-region, 74...First oxide superconductor electrode, 75...Second oxide superconductor electrode, 76... Cutting die for lift-off, 91...
...n-type GaAs substrate, 92...P+ region,
93... P-type region, 94... First superconducting electrode, 95... Second superconducting electrode, 96
・・・・・・Cutting die for lift-off, 101・・・・・・
Gate electrode, 102... Gate insulating film, 103
... Silicon substrate, 104 ... Superconducting electrode, 111 ... Semiconductor substrate, 112 ...
...Superconducting electrode, 113...Gate oxide film, 1
14...Gate electrode. Agent Patent Attorney Uchi Hara On Piece J Zuzu 4 Figure θ 24/y8iθ Waka 7 Figure I θ, 219.4 17.6 728 l
Sauce dray stains (English No. 8, Figure 7 erased

Claims (4)

[Claims] (1) A first semiconductor layer of one conductivity type, a second semiconductor layer of another conductivity type provided on the first semiconductor layer, and a second semiconductor layer of another conductivity type provided on the first semiconductor layer;
first and second electrodes made of a superconductor provided in contact with the surface of the semiconductor layer and spaced apart from each other; and a third electrode electrically connected to the first semiconductor layer. A semiconductor-coupled superconducting circuit device characterized by (2) The second semiconductor layer has a high concentration region under the first and second electrodes and a low concentration region between the first and second electrodes. Semiconductor-coupled superconducting circuit device (3) The second semiconductor layer has a deep impurity region under the first and second electrodes and a shallow impurity region between the first and second electrodes. Semiconductor-coupled superconducting circuit device (4) The second semiconductor layer has a deep region with high concentration under the first and second electrodes and a shallow region with low concentration between the first and second electrodes. Semiconductor-coupled superconducting circuit device (5) according to item 1: forming a lift-off die in contact with the main surface of the first semiconductor layer of one conductivity type, and using the die as a doping mask. forming a second semiconductor layer of a different conductivity type within the first semiconductor layer; and after depositing a superconductor film on the second semiconductor layer and the cutting die, using the cutting die; selectively providing the superconductor film on the second semiconductor layer by patterning the superconductor film using a lift method, and then removing the superconductor film and removing the exposed superconductor film. forming a third semiconductor layer of the other conductivity type below the surface of the first semiconductor layer.