JPH0178450U - - Google Patents
Info
- Publication number
- JPH0178450U JPH0178450U JP1987173797U JP17379787U JPH0178450U JP H0178450 U JPH0178450 U JP H0178450U JP 1987173797 U JP1987173797 U JP 1987173797U JP 17379787 U JP17379787 U JP 17379787U JP H0178450 U JPH0178450 U JP H0178450U
- Authority
- JP
- Japan
- Prior art keywords
- error
- data
- check code
- forming means
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Description
第１図は本考案の基本的構成を示す図、第２図
は本考案の実施例の主要部の構成を示す図、そし
て、第３図は本考案の実施例における送信フレー
ムの構成図である。
（符号の説明）、１……データ形成手段、２…
…誤りチエツク・コード付加手段、１０……論理
リンク層制御回路、１１……種類コード・レジス
タ、２０……媒体アクセス層制御回路、２１……
エラー指定レジスタ、２２……比較回路、２３…
…エラー発生回路、３０……エラー発生設定レジ
スタ。
Figure 1 is a diagram showing the basic configuration of the present invention, Figure 2 is a diagram showing the configuration of the main part of an embodiment of the invention, and Figure 3 is a diagram showing the configuration of a transmission frame in an embodiment of the invention. be. (Explanation of symbols), 1... data forming means, 2...
...Error check code addition means, 10...Logic link layer control circuit, 11...Type code register, 20...Medium access layer control circuit, 21...
Error specification register, 22... Comparison circuit, 23...
...Error generation circuit, 30...Error generation setting register.
Claims (1)
と、該データ形成手段１から受けたデータに誤り
チエツク・コードを付加する誤りチエツク・コー
ド付加手段２とを有してなる送信装置において、 前記データ形成手段１は、送信すべきデータの
種類を示すコードを該データと共に送出し、 前記誤りチエツク・コード付加手段２は、前記
誤りチエツク・コードを付加する際に意図的にエ
ラーを発生させるエラー発生回路２３と、該エラ
ーを発生すべきデータの種類を設定するエラー指
定レジスタ２１と、該エラー指定レジスタ２１の
内容と前記データ形成手段１から送出された送信
すべきデータの種類とを比較して一致するとき前
記エラー発生回路２３を作動させる比較回路２２
とを有することを特徴とする送信装置。[Scope of claim for utility model registration] Data forming means 1 for forming data to be transmitted
and an error check code adding means 2 for adding an error check code to the data received from the data forming means 1, wherein the data forming means 1 determines the type of data to be transmitted. The error check code adding means 2 includes an error generating circuit 23 that intentionally generates an error when adding the error check code, and a code indicating that the error should be generated. An error designation register 21 for setting the type is compared with the content of the error designation register 21 and the type of data to be transmitted sent from the data forming means 1, and when they match, the error generation circuit 23 is activated. circuit 22
A transmitting device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987173797U JPH0178450U (en) | 1987-11-16 | 1987-11-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987173797U JPH0178450U (en) | 1987-11-16 | 1987-11-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0178450U true JPH0178450U (en) | 1989-05-26 |
Family
ID=31465687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987173797U Pending JPH0178450U (en) | 1987-11-16 | 1987-11-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0178450U (en) |
-
1987
- 1987-11-16 JP JP1987173797U patent/JPH0178450U/ja active Pending
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