JPS63195437U - - Google Patents
Info
- Publication number
- JPS63195437U JPS63195437U JP8586587U JP8586587U JPS63195437U JP S63195437 U JPS63195437 U JP S63195437U JP 8586587 U JP8586587 U JP 8586587U JP 8586587 U JP8586587 U JP 8586587U JP S63195437 U JPS63195437 U JP S63195437U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- parity
- parity check
- register
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Detection And Correction Of Errors (AREA)
- Retry When Errors Occur (AREA)
Description
第１図は、この考案による一実施例を示すパリ
テイチエツクシステムのブロツク図、第２図は従
来のパリテイチエツクシステムのブロツク図であ
る。
図において、１は送信回路、２は受信回路、３
はパリテイチエツク回路、４はステータスレジス
タ、５はＭＰｕ、６はリトライ設定レジスタ、７
はリトライカウンタ、８は比較回路、９は制御回
路である。なお、図中同一符号は同一、又は相当
部分を示す。
FIG. 1 is a block diagram of a parity check system showing one embodiment of this invention, and FIG. 2 is a block diagram of a conventional parity check system. In the figure, 1 is a transmitting circuit, 2 is a receiving circuit, and 3 is a transmitting circuit.
is a parity check circuit, 4 is a status register, 5 is MPu, 6 is a retry setting register, 7
is a retry counter, 8 is a comparison circuit, and 9 is a control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
を行なうパリテイチエツク回路と、このパリテイ
チエツク回路からの出力を受け、プロセツサにパ
リテイ状態を伝える第１のレジスタと、上記プロ
セツサにより再送回数が設定される第２のレジス
タと、上記パリテイチエツク回路によりパリテイ
エラーのとき、送信回路に再送を要求し、上記第
１のレジスタにエラー状態を書き込む制御回路と
、この制御回路によつて再送要求の回数をカウン
トするカウンタと、このカウンタと上記第２のレ
ジスタとの出力を比較する比較回路とを備え、上
記プロセツサによつて設定された再送回数分のエ
ラーが発生したときにパリテイエラーとすること
を特徴とするデータ読出回路。 A parity check circuit receives the transmitted data and performs a parity check; a first register receives the output from the parity check circuit and transmits the parity status to the processor; and the processor sets the number of retransmissions. a control circuit that requests the transmission circuit to retransmit when a parity error occurs by the parity check circuit and writes an error state to the first register; It is equipped with a counter that counts the number of times, and a comparison circuit that compares the output of this counter and the second register, and determines a parity error when an error equal to the number of retransmissions set by the processor occurs. A data read circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8586587U JPS63195437U (en) | 1987-06-01 | 1987-06-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8586587U JPS63195437U (en) | 1987-06-01 | 1987-06-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63195437U true JPS63195437U (en) | 1988-12-15 |
Family
ID=30941656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8586587U Pending JPS63195437U (en) | 1987-06-01 | 1987-06-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63195437U (en) |
-
1987
- 1987-06-01 JP JP8586587U patent/JPS63195437U/ja active Pending
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