JPH0179138U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an internal memory monitor circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1...Target microprocessor, 2...
...Memory, 3, 4, 8...Buffer, 5...Memory for monitoring, 6...Bus control circuit, 7...Data bus, 9...Monitor circuit in emulator.

Claims (1)

[Claim for Utility Model Registration] The target microprocessor is a target microprocessor that has an internal memory, and a monitor memory is prepared to monitor the internal memory, and when a write operation is executed to the internal memory, the monitor memory is When the microprocessor writes data or reads data, the microprocessor reads its own internal memory and also causes the emulator to output data from the monitor memory. A bus control circuit that provides the highest priority interrupt signal to the target microprocessor when a reset signal is input to the target microprocessor and controls switching of data bus connections, and a program executed by the target microprocessor. , and a memory in which an interrupt processing routine for writing an initial value, which is the highest priority interrupt processing from the bus control circuit, is stored, and when a reset signal is input to the target microprocessor, the initial value of the monitoring memory is stored. An internal memory monitor circuit characterized in that the internal memory is written to match the initial value of the internal memory.