JPH0179151U - - Google Patents
Info
- Publication number
- JPH0179151U JPH0179151U JP17491687U JP17491687U JPH0179151U JP H0179151 U JPH0179151 U JP H0179151U JP 17491687 U JP17491687 U JP 17491687U JP 17491687 U JP17491687 U JP 17491687U JP H0179151 U JPH0179151 U JP H0179151U
- Authority
- JP
- Japan
- Prior art keywords
- week
- day
- schedule data
- input means
- schedule
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Electric Clocks (AREA)
- Calculators And Similar Devices (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
第１図は本考案の一実施例の回路構成を示す図
、第２図は第１図におけるＲＡＭの構成を示す図
、第３図は上記実施例の動作の概要を示すジユネ
ラルフローチヤート、第４図は上記実施例の表示
変遷を示す図、第５，６図は第４図におけるキー
処理を詳細に示すフローチヤート、第７図は第４
図における計時処理を詳細に示すフローチヤート
である。
１……ＲＯＭ、２……ＲＯＭアドレス制御部、
３……ＲＡＭ、４……インストラクシヨンデコー
ダ、５……演算回路、６……ラツチ、７……発振
器、８……タイミングジエネレータ、９……キー
入力部、１０……分周回路、１１……表示部、Ｃ
……日付レジスタ、ｎ……既設定スケジユール数
レジスタ、Ｍ……モードカウンタ、ｍ……曜日指
示カウンタ、ｌ……行アドレス数記憶レジスタ、
ＳＭ……スケジユール記憶エリア、Ｔ……時刻計
時レジスタ。
FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the RAM in FIG. 1, and FIG. 3 is a general flow chart showing an overview of the operation of the above embodiment. FIG. 4 is a diagram showing the display transition of the above embodiment, FIGS. 5 and 6 are flowcharts showing details of key processing in FIG. 4, and FIG.
2 is a flowchart showing details of the time measurement process in the figure. 1...ROM, 2...ROM address control unit,
3...RAM, 4...Instruction decoder, 5... Arithmetic circuit, 6... Latch, 7... Oscillator, 8... Timing generator, 9... Key input section, 10... Frequency dividing circuit, 11...Display section, C
...Date register, n...Preset schedule number register, M...Mode counter, m...Day of the week instruction counter, l...Line address number storage register,
SM...Schedule storage area, T...Time clock register.
Claims (1)
と、スケジユールデータを入力するスケジユール
データ入力手段と、前記曜日入力手段により入力
された曜日と前記スケジユールデータ入力手段に
より入力されたスケジユールデータとを記憶する
記憶手段と、この記憶手段に記憶された曜日とス
ケジユールデータとを対応ずけて表示する表示手
段とを具備したことを特徴とするスケジユール表
示装置。 A day of the week input means for inputting a specific day of the week of a specific week, a schedule data input means for inputting schedule data, and a memory for storing the day of the week input by the day of the week input means and the schedule data input by the schedule data input means. What is claimed is: 1. A schedule display device comprising: storage means for storing the day of the week; and display means for displaying the day of the week and schedule data stored in the storage means in correspondence with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17491687U JPH0179151U (en) | 1987-11-16 | 1987-11-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17491687U JPH0179151U (en) | 1987-11-16 | 1987-11-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0179151U true JPH0179151U (en) | 1989-05-26 |
Family
ID=31466746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17491687U Pending JPH0179151U (en) | 1987-11-16 | 1987-11-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0179151U (en) |
-
1987
- 1987-11-16 JP JP17491687U patent/JPH0179151U/ja active Pending
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