JPH0227224U - - Google Patents
Info
- Publication number
- JPH0227224U JPH0227224U JP10234888U JP10234888U JPH0227224U JP H0227224 U JPH0227224 U JP H0227224U JP 10234888 U JP10234888 U JP 10234888U JP 10234888 U JP10234888 U JP 10234888U JP H0227224 U JPH0227224 U JP H0227224U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- data
- digit
- function
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013500 data storage Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 1
Landscapes
- Calculators And Similar Devices (AREA)
- Input From Keyboards Or The Like (AREA)
Description
第１図は本考案の一実施例の外観を示す図、第
２図は、上記実施例の回路構成を示す図、第３図
は第２図におけるＲＡＭの構成を示す図、第４図
は本実施例の動作の概要を示すジエネラルフロー
チヤート、第５図は上記ジエネラルフローチヤー
ト中のキー処理を詳細に示すフローチヤート、第
６図はデリート処理およびインサート処理におけ
る表示の変遷を示す図である。
１……時計ケース、２……液晶表示パネル、５
……ＲＯＭ、６……ＲＯＭアドレス制御部、７…
…ＲＡＭ、８……インストラクシヨンデコーダ、
９……演算回路、１０……ラツチ回路、１１……
発振器、１２……タイミングジエネレータ、１３
……キー入力部、１４……分周回路、１５……表
示部、１６……ブザー、ＤＲ……表示レジスタ、
Ｔ……計時レジスタ、Ｍ……モードレジスタ、Ｆ
……状態フラグ、Ｃ……桁指定レジスタ、Ｐ……
アドレスポインタ、ＤＢ……データバンク部、Ｇ
……機能指定レジスタ。
FIG. 1 is a diagram showing the appearance of one embodiment of the present invention, FIG. 2 is a diagram showing the circuit configuration of the above embodiment, FIG. 3 is a diagram showing the configuration of the RAM in FIG. 2, and FIG. 4 is a diagram showing the configuration of the RAM in FIG. A general flowchart showing an overview of the operation of this embodiment, FIG. 5 is a flowchart showing details of key processing in the general flowchart, and FIG. 6 is a diagram showing changes in display during delete processing and insert processing. It is. 1... Watch case, 2... Liquid crystal display panel, 5
...ROM, 6...ROM address control section, 7...
...RAM, 8...Instruction decoder,
9... Arithmetic circuit, 10... Latch circuit, 11...
Oscillator, 12... Timing generator, 13
...Key input section, 14...Frequency dividing circuit, 15...Display section, 16...Buzzer, DR...Display register,
T...Time register, M...Mode register, F
...Status flag, C...Digit specification register, P...
Address pointer, DB...data bank section, G
...Function specification register.
Claims (1)
が表示される表示部の桁を指定する桁指定スイツ
チと、該スイツチの操作によつて指定されている
桁に、予め定められたデータ順に従つて、操作さ
れる度にデータを、順次、変更して入力していく
データ変更スイツチとを操作して行なうデータ記
憶装置において、 上記桁指定スイツチおよびデータ変更スイツチ
以外の第３のスイツチと、 この第３のスイツチの操作を受け、上記桁指定
スイツチを、順次、桁指定スイツチ、デリートキ
ーおよびインサートキーとして機能させる機能変
換手段とを備えたことを特徴とするデータ記憶装
置。[Claims for Utility Model Registration] Data input and correction can be performed in advance using a digit designation switch that specifies the digit of the display section where the input data is displayed, and the digit designated by the operation of the switch. In a data storage device that operates a data change switch that sequentially changes and inputs data each time it is operated according to a predetermined data order, the 3, and function converting means that receives the operation of the third switch and sequentially causes the digit designation switch to function as a digit designation switch, a delete key, and an insert key. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10234888U JPH0227224U (en) | 1988-08-03 | 1988-08-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10234888U JPH0227224U (en) | 1988-08-03 | 1988-08-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227224U true JPH0227224U (en) | 1990-02-22 |
Family
ID=31332177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10234888U Pending JPH0227224U (en) | 1988-08-03 | 1988-08-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227224U (en) |
-
1988
- 1988-08-03 JP JP10234888U patent/JPH0227224U/ja active Pending
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