JPH01808A - semiconductor circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor circuit, and is particularly used for a so-called source follower circuit.

[Conventional technology]

A circuit called a source follower circuit is widely used as an output buffer of a semiconductor circuit. FIG. 4(a) is a circuit diagram of an example of such a conventional circuit, in which an output field effect transistor (
A field effect transistor (FET) 2 is connected to the FET 1 as a current source. Here, the FET 2 can be replaced by a resistor formed on a semiconductor substrate, but the larger the resistance value, the closer the voltage gain is to 1, so it is preferable, and a field effect transistor is usually used. Normally, it is not possible to increase the resistance value with the voltage (2 to 10 V) used as the power supply voltage for integrated circuits.
If you try to increase the resistance value, the power supply voltage will inevitably increase.

Therefore, the circuit configuration shown in Figure 4 (a) is generally adopted, but this has the following characteristics.In other words, the source follower circuit has high input impedance, low output impedance, and It is characterized by a voltage gain of approximately 1 (actually a little lower than 1).

Therefore, when used as the output buffer 7 of an amplifier circuit in an IC, for example, the signal from the previous stage circuit is outputted without much attenuation of the voltage amplitude, and the driving ability of the load can be improved.

[Problem that the invention seeks to solve]

However, FETs with predetermined characteristics on semiconductor substrates
is not easy to form. Therefore, variations appear in element constants such as mutual conductance g, and therefore output impedance Z. , variations also occur.

In order to compensate for such variations in element constants, it is conceivable to provide an impedance adjustment terminal as shown in FIG. 4(b), for example.

This is done by connecting the gate terminal of FET2 to the impedance adjustment terminal and making the gate potential of FET2 variable from outside the chip, thereby adjusting the gate-source voltage Vg of FET2 and changing the mutual conductance q and, in turn, the output impedance Z. . This is an attempt to adjust the

However, if this is done, noise is likely to be superimposed on the impedance adjustment terminal, and the output impedance Z. becomes difficult to stabilize.

Therefore, the present invention provides an F for a current source formed on a semiconductor substrate.
It is an object of the present invention to provide a semiconductor circuit whose output impedance can be easily adjusted even if variations occur in the element constants of an ET, and which is stable against noise.

[Means for solving problems]

A semiconductor circuit according to the present invention includes a semiconductor substrate, an output FET formed on the semiconductor substrate to operate by inputting a signal from a predetermined pre-stage circuit, and a drain terminal connected to a source terminal of the output FET. at least two current source FETs formed on a semiconductor substrate with their respective gate terminals and drain terminals short-circuited; It is characterized in that at least one is selected and connected to the power supply terminal.

[Effect]

Since the semiconductor circuit according to the present invention is configured as described above, by selecting at least one desired current source FET from at least two current source FETs formed on a semiconductor substrate and connecting it to the output FET. , it becomes possible to adjust the output impedance by compensating for variations in element constants.

〔Example〕

Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 1 to 3 of the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

First, prior to a specific description of the embodiments, the present invention will be described in detail as follows. Generally, the output impedance Z in a source follower circuit as shown in FIG. Considering FET2 as an ideal constant current source, Zo~, 1/(gm1+gdsl)
”・(1) Here, qIIll
is the transconductance of FET1, and 'dsl is the drain conductance of FET1. And since the normal condition is gllll>Q dsl, the value of the output impedance Zo is as follows:
The mutual conductance gII11 is the dominant factor.

That is, the above equation (1) is Z. ~1/gI111.

It can be expressed as Here, K1 is a proportionality constant, W,1 is the gate width of FET1, and ■0,1 is the FE
TI gate-source voltage, vthl is FET1
is the threshold voltage of And the gate-source voltage
. , 1 are larger than the threshold voltage Vth1, the gate-source voltage V0,1 is the dominant factor in determining the value of the drain current ■d.

Therefore, from the above equations (1) and (2), 49 reciprocal conductance g1. The relationship between I11 and drain current ■d is determined as gm 1-a I d/c7 V gsl.

Therefore, from the above equation (3), it can be seen that the mutual conductance gm1 can be controlled by controlling the drain current Id, and roughly from the above equation (1), the mutual conductance gII
It can be seen that by controlling 11, the output impedance Zo can be controlled.

On the other hand, for the drain current Id, it is FET2.

Here, K2 is a proportionality constant, Wg2 is necessarily the gate width of FET2, and Vth2 is the threshold 1 direct voltage of FET2. Therefore, from the above equation (4), the drain current 1d is proportional to the gate width Wg2 of the FET2.

As a result of the above, if the gate width Wg2 of FET2 is increased, the output impedance Z will be increased. On the other hand, if the gate width Wg2 of FET2 is made small, the output impedance Z can be made small. It turns out that it is possible to make it larger. The present invention utilizes this, and the output impedance Z is adjusted by adjusting the gate width of FET2 during constant excitation. This is necessary if you are trying to adjust the That is, as shown in FIG. 3, when the gate width W, 2 of FET 2 is necessarily 150 μm, on average (g, = 100%
(when it is an average value) output impedance Z. Even if a 50Ω value is obtained, if there is a ±30% variation in the mutual conductance g, the output impedance Z. , there appears a variation as indicated by the symbol A in the figure. Therefore, when the mutual conductance g varies in the direction of decreasing, the gate width W of FET2
When g2 is narrowed to 140 μm, 130 μm, etc. during uniform excitation, and the mutual conductance g is varied in the direction of increasing, the gate width Wg1 of FET2 is set to 16
The width is increased to 0 μm, 170 μm, etc. during constant excitation.

This results in output impedance Z.

adjustment becomes possible.

Next, an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a circuit diagram of an embodiment. As shown in the figure, five current source FETs 21 are connected to the source terminal of output FET 1.
~25 are connected in parallel.

The gates and sources of the FETs 2'1 to 25 are short-circuited, and the source terminals of the FETs 2'1 to 25 are connected to negative power terminals V1 to V, 35, respectively.

SI Here, the gate width W, 21 of the FET 21 is, for example, W, 2
1=130! l m, and FET22~2
4, the gate width Wg22 to W925 is, for example, WCl22.
Connect the power supply terminal V3,1 to the power supply first, then connect the FET2
By selectively connecting the negative power supply terminals 332 to 8, 5 for 2 to 25 to the power supply, the overall gate width Wg2
can be changed when uniformly excited. That is, for example, if only the negative power supply terminal V, 32 is selected, the entire gate width Wg2 becomes Wg2 = Wg21 + Wg22 = (130 + 10> μm = 140I1m), and if all the negative power supply terminals VSS2 to V8, 5 are selected, The overall gate width Wg2 is wg2 = Wg21 +wg22 +wg23 +wg2
4 +wg25= (130+10X4) μm −170 μm. Therefore, the gate width when uniformly excited is 130 to 170μ.
The output impedance Z can be changed within the range of m by adjusting the transconductance q. can be adjusted.

The present invention is not limited to the embodiments described above, and various modifications are possible.

For example, the number of FETs for adjusting the gate width is not limited to four, but may be any number as long as it is one or more. In addition, FE for adjustment
The gate widths of T may be set differently.

〔Effect of the invention〕

As described above in detail, in the present invention, at least one desired current source FET is selected from at least two current source FETs formed on a semiconductor substrate and connected to an output FET, thereby controlling the current source FET. Since the gate width can be changed during uniform excitation, the output impedance can be easily adjusted even if there are variations in the element constants of the current source FETs formed on the semiconductor substrate, and the output impedance can be easily adjusted. It is also possible to provide stable semiconductor circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor circuit according to an embodiment of the present invention,
FIG. 2 is a circuit diagram for explaining the present invention in detail, FIG. 3 is a diagram for explaining the relationship between gate width and output impedance, and FIG. 4 is a circuit diagram for explaining the prior art. F E T 1... Output field effect transistor, F
ET2. FET21 to FET25... Field effect transistors for current sources. Patent Applicant Sumitomo Electric Industries Co., Ltd. Patent Attorney Yoshiki Hase Explanatory diagram of the principle Fig. 2

Claims (1)

[Claims] 1. A semiconductor substrate and an output FE formed on the semiconductor substrate to operate by inputting a signal from a predetermined pre-stage circuit.
T, and at least two current source FETs formed on the semiconductor substrate with respective drain terminals connected to the source terminal of the output FET and respective gate terminals and drain terminals short-circuited, A semiconductor circuit characterized in that at least one of the drain terminals of at least two current source FETs is selected and connected to a power supply terminal. 2. The at least two current source FETs include one FET with a predetermined gate width and at least one FET with a gate width narrower than this FET, and at least the FET with the predetermined gate width is connected to the power supply terminal. A semiconductor circuit according to claim 1, characterized in that: