JPH01814A - Complementary signal output circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an Aiura signal output circuit that obtains complementary signals that are in-phase and inverted 4 (1) to an input signal.

(Prior Art) FIG. 9 is a diagram showing the configuration of a complementary signal output circuit for subtracting by 1% complementary signals that are used as clock signals for logic circuits and have opposite phases to each other.

The complementary signal output circuit shown in FIG. 9 is constituted by an inverter circuit ll-I4 made of CMOS, for example.
The human input signal (IN) is received by the inverter circuit 11 and inverted, and the output of the inverter circuit 11 is transferred to the inverter circuit ■
The output of the inverter circuit T2 is further inverted by the inverter circuit 13, and the output of the inverter circuit I is inverted by the inverter circuit I.
−+ output as a complementary signal φ with opposite phase to the input signal (
I'm q. On the other hand, the output of the inverter circuit 11 is inverted by the inverter circuit 14, and the output of the inverter circuit I4 is made into a complementary signal φ having the same phase as the input signal.

Therefore, in such a configuration, the complementary signal φ is transmitted to the odd-numbered inverter circuits It, 12, 12, . i! by I3 7, whereas the complementary signal φ is an even-numbered stage inverter circuit 1+ connected in cascade to the input signal.

[J for 4 is obtained. In other words, the complementary signal φ is output with a delay time of two inverter circuit stages relative to the input signal, whereas the complementary signal φ is output with a delay time of three stages of inverter circuits relative to the input signal. Therefore, the complementary signal φ is as shown in the operation waveform diagram of FIG.
This results in a delay of one stage of the inverter circuit compared to the complementary signal φ.

(Problems to be Solved by the Invention) As explained above, in the complementary signal output circuit as shown in FIG. Since the signal φ is provided through inverter circuits having a different number of stages than the human input signal, there is a problem that the complementary signal φ and the complementary signal φ have a switching interval of n.

Therefore, the present invention has been made in view of the above, and its purpose is to provide switching for an input signal of a complementary signal having the same phase as the input signal and a complementary signal having the opposite phase to the input signal. It is an object of the present invention to provide a complementary signal output circuit which can reduce the time to the same level with a simple configuration.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a method in which an input signal is received by a first-stage inverting circuit among a plurality of inverting circuits connected in series, A complementary signal output circuit is configured to provide a complementary signal that is in phase with the input signal to the output terminal of the even-numbered inversion circuit, and a complementary signal that is in phase opposite to the input signal to the output terminal of the odd-numbered inversion circuit. VC connected between the output/J terminal of the inverting circuit of even-numbered stages 1 and the power supply, whose conduction is controlled by the in-phase signal.
and/or a transistor connected between the output terminal of the odd-numbered stage inverting circuit and the power supply, the conduction of which is controlled by a signal having a phase opposite to that of the input signal.

(Function) In the above configuration, the present invention conducts the transistors connected between the output end of the even-numbered stage inverting circuit and the power supply by a signal that is in phase with the input.
Alternatively, by controlling the conduction υ of the transistors connected between the output end of the odd-numbered inverting circuit and the power supply using a signal that is in antiphase with the input signal, one or both of the complementary signals that are in antiphase with each other can be It is designed to compensate for switching operations.

(Example) Hereinafter, the invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a complementary signal output circuit according to an embodiment of the present invention.

The complementary signal output circuit shown in FIG. 1 includes cascade-connected inverter circuits 1s, Ia, and ly and an NPN bipolar transistor Q1, and can be used when the load of complementary signals φ and φ is relatively light. This shows the configuration.

The inverter circuit I5 receives the input signal (IN>, inverts it, and supplies the output) j to the inverter circuit 1θ.

Inverter circuit 6 receives the output of inverter circuit 15, inverts it, and provides a complementary signal φ that is in phase with the input signal. Inverter circuit I7 receives complementary signal φ that is the output of inverter circuit I6, inverts it, and provides complementary signal φ having an opposite phase to the input signal.

The bipolar transistor Q1 has its base connected to the output end of the inverter circuit I5 via a current limiting resistor R, its collector connected to the power supply, and its emitter connected to the output end of the inverter circuit I7. .

In such a configuration, when the input signal falls from a high level state to a low level state, the inverter circuit r5
The output changes from a low level state to a high level state. When the output of the inverter circuit I5 shifts from the low level state to the high level state, the output of the inverter circuit I5 is inverted by the inverter circuit IB, and the complementary signal φ falls from the high level state to the low level state.

On the other hand, when the output of the inverter circuit I5 rises from a low level state to a high level state, the bipolar transistor Q1 changes from a non-conductive state to a conductive state. This results in
The complementary signal φ changes from a low level state to a high level state (f4
/\Starts to stand up. Then, when the output of the inverter circuit I6, that is, the complementary signal φ changes from the high level state to the low level state, the complementary signal φ is inverted by the inverter circuit 17, and the complementary signal φ rises from the low level state to the high level state. The increase also takes place in the inverter circuit 17.

That is, the falling of the complementary signal φ by Nγ and the rising of the complementary signal φ both begin to be performed by the output of the inverter circuit I5. Therefore, the time difference between the rising edge of complementary signal φ and the falling edge of complementary signal φ (
The skew]-) becomes small, and can be made much smaller than the skew of the complementary signals φ and φ generated by the complementary signal output circuit shown in FIG.

Furthermore, the delay time of the complementary signal φ with respect to the input signal is approximately the delay time of two stages of inverter circuits, and can be made faster than the complementary signal φ jq in the configuration shown in FIG.

FIG. 2 is a diagram showing an example in which the inverter circuit +5, 16, 17 constituting the complementary signal output circuit shown in FIG. 1 is configured with 0MO8.

In FIG. 2, the inverter circuit 15 is P M○y;
P'! and NMO3NI, and Invar/I
l [ijl path 16 is PMO8P2 and N M OS N
2, the inverter circuit I7 is composed of PM
It is composed of O8P3 and NMOSN3.

Even in such a configuration, the same effect as shown in FIG. 1 can be obtained, and the inverter circuit I
5. By making Ie and Iy 0MO3° (14°), it is possible to reduce power consumption.

FIG. 3 is a diagram showing the configuration of a complementary signal output circuit in which the inverter circuits Is, Is, and I7 are configured with 0 MO8, similar to the complementary signal output circuit shown in FIG.

The complementary signal amount horn circuit shown in FIG. 3 is constructed by connecting an NMO8N4 whose conduction is controlled by an input signal between the NMO8N3 constituting the inverter circuit 17 and the ground to the complementary signal output circuit shown in FIG. The composition of Haku is the same as in Figure 2, and it is shown with the same - sign month.

The feature of this complementary signal output circuit is that in the complementary signal output circuit shown in FIG.
After the output of Q1 and NMO8N3 change from a low level to a high level and until NMO8N3 changes from a conductive state to a non-conductive state, there is a period in which both bipolar transistor Q1 and NMO8N3 are conductive. When the input signal falls from a high level state to a low level state, the normal current flowing to the ground via the bipolar transistor Q1 and NMO8N3
4 is changed from a conductive state to a non-conductive state and is covered for prevention.

Therefore, even in such a configuration, the skew between the rising edge of the complementary signal φ and the falling edge of the complementary signal φ can be reduced with respect to the falling edge of the input signal.

FIG. 4 is a circuit diagram showing the configuration of a complementary signal output circuit according to another embodiment of the invention. The complementary signal output circuit shown in the figure is composed of an inverter circuit I8 and 0MO8. In the embodiments described below, components with the same reference numerals have the same functions, and their explanations will be omitted.

In FIG. 4, the output of an inverter circuit I8 that receives an input signal (IN) and inverts it is connected to a PMO8P5 whose terminal is connected to the output of the inverter circuit Is and whose source is connected to the power supply. , an inverter circuit I consisting of NMO3N5 whose gate terminal is connected to the output of the inverter circuit I8 and whose source terminal is connected to the ground, and which outputs a complementary signal φ from mutually connected drain terminals.
9 is connected. The output of this inverter circuit I9 is connected to the source of NMO8N6 whose gate terminal is given an input signal, whose train terminal is connected to the power supply, and whose gate terminal is given an eight signal, and whose drain terminal is connected to the source of NMO8N6. is connected to the source terminal of PMO3P6, which is connected to ground.

In addition, the input of the inverter circuit 18 includes PMOS P7 and N~+08N7, which receive input signals at their respective gate terminals and whose respective drain terminals are connected to each other.
An inverter circuit 1+o is connected to output a complementary signal φ from a drain terminal connected to an H terminal. The output of this inverter circuit 110 is connected to the source terminal of NMO8N8 whose gate terminal is connected to the output of the inverter circuit 18 and whose train terminal is connected to the power supply, and whose gate terminal is connected to the output of the inverter circuit I8. The source terminal of PMO8P8, whose drain terminal is connected to ground, is connected to the source terminal of PMO8P8.

In such a configuration, first of all, the input signal is [
The case of rising from the 1-U level to the High level will be explained.

When the input signal starts to rise from 0U level to high level, NMO8N6. N7 becomes conductive, and as a result, the complementary signal φ starts to rise from a low level to a high level, and at the same time, the complementary signal φ starts to fall from a high level to a low level. Then, when the output of the inverter circuit 18 changes from high level to low level, PM
O8P5 and P8 become >4 pieces. For this reason, the rising speed of the complementary signal φ and the falling speed of the complementary signal φ are accelerated, and the rising and falling waveforms become sharp. Furthermore, the complementary signal φ is raised to the power supply potential by PMO8P5.

Next, a case where the input signal falls from high level to low level will be explained. When the input signal starts falling from high level to low level, PMO8P6. P7 becomes conductive, and as a result, the complementary signal φ starts to fall from the high level to the low level, and at the same time, the complementary signal φ starts to rise from the low level to the high level. Then, when the output of inverter circuit ①8 goes from L1 low level to high level, NMO8N5. N8 becomes conductive. Therefore, the rising speed of the complementary signal φ and the falling speed of the complementary signal φ become faster, and the rising and falling waveforms become sharper.

In this way, one complementary signal is not used as an input signal to obtain the other complementary signal, and the rNMO8
N6. N7 or PMO8P6. P7 are made conductive at the same time, and PMO8P5. P8 or NMO8
N5. Since N8 was made conductive at the same time,
It becomes possible to make the potentials at the intersections of the rising and falling points of the complementary signals φ and φ almost the same, and it becomes possible to make the switching times of the complementary signals φ and φ with respect to the input signals almost the same. Furthermore, inverter circuit 1
Since PMO8P8 and NMO3N8 are provided at the output of +o, the complementary signal φ also rises.

The falling waveform can be sharpened.

FIG. 5 is a circuit diagram showing the configuration of a complementary signal output circuit according to still another embodiment of the present invention. The complementary signal output circuit shown in the figure is the inverter circuit [8, 19
, 110 and an NPN type bipolar transistor.
Q2 and Q3 (referred to as BTJ).

In FIG. 5, BrO3 has an input signal applied to its base terminal, and a collector terminal connected to a power supply.
The emitter terminal is connected to the output terminal of the inverter circuit I9. This BrO3 is controlled to be conductive by an input signal, and causes the complementary signal φ to rise.

B 1' Q 3 has its base terminal connected to the output end of the inverter circuit 1B, its collector terminal connected to the power supply, and its emitter terminal connected to the output end of the inverter circuit 1+o. This B-1-03 is made conductive by the output of the inverter circuit 8, and causes the complementary signal φ to rise.

In such a configuration, when the input signal starts rising from low level to high level, BrO3 and NMO3
N7 becomes conductive, the complementary signal φ starts to rise, and the complementary signal φ starts to fall. Then, when the output of the inverter circuit I8 falls from the high level to the low level, the PMO8P5 becomes conductive, and the complementary signal φ rises. In this way, when the input signal rises, NMO8N7 becomes conductive, whereas 1) M
OS P 5 becomes conductive at the delay time of one stage of the inverter circuit I8, but in order to compensate for this delay, -(BrO2 is made conductive at the rise of the input signal, and the complementary signal φ is being launched.

Next, when the input signal begins to fall from the high level to the low level, P to l08P7 become conductive and the 8 complementary 1 old signal φ starts to rise. IshiC, inverter circuit 18
When the output of NMO8 goes from low level to high level,
N5 becomes conductive and the complementary signal φ begins to fall.

Furthermore, at the same time, BrO3 becomes conductive and the complementary signal φ rises to 1.

FIG. 6 is a diagram showing the simulation result of complementary signals φ, φ with respect to the input signal in the circuit shown in FIG. As shown in FIG. 6, even in the p1 path configuration shown in FIG. 5, the complementary signal φ.

It becomes possible to substantially match the potentials at the intersections of the rising edges of φ and the rising edges of F, and it is possible to cover the switching times almost the same. Furthermore, the inverter circuit 19. A bipolar transistor is installed at the output terminal of I+O to start up the complementary signals φ and φ. It can be made to fit the length of the seat.

FIG. 7 is a circuit diagram showing the configuration of a complementary signal output circuit according to still another embodiment of the present invention. The complementary signal output circuit shown in the same figure has an inverter circuit (qEt) of the complementary signal output circuit shown in FIG. NP
Inverter circuit 1 includes N-type BrO3 and BrO5.
B as PMO8P10 and N! It is characterized by being constructed with vlO8N10. Further, this complementary signal output circuit inputs the input signal IN to the inverter circuit 1B via the input circuit 11.
A complementary signal φ having the opposite phase to the input signal is obtained from the output terminal of the inverter circuit I9, and a complementary signal φ having the same phase as the input signal is obtained from the output terminal of the inverter circuit 110. 7 input circuit 11 is PMO8P
I 1. Pl 2, N~? 08N11. Nl 2 and 8
When the input signal goes from high level to low level, PMO8P11 . Pi 2 and B
rO6 becomes conductive, and a high-level complementary signal is applied to the input terminal of inverter circuit 8. Also, when the input signal goes from low level to high level, NMO8N11
, N12 become conductive, and supply low-level complementary signals to the input of the inverter circuit I8. That is, the input circuit 11 inverts the input signal to the inverter circuit I8.
is given to the input of

BrO3 is connected between the output end of the inverter circuit I9 and ground, and the base terminal is NMO8N connected in series between the output end of the inverter circuit 1B and the ground.
13. It is connected to the connection point of N14. NMO8N
13 is controlled to be conductive by the output of the inverter circuit I8, and NMO8N14 is controlled to be conductive by the output of the input circuit 11.

BrO5 is connected between the output end of the inverter circuit T+o and the ground, and its base terminal is connected to the inverter circuit 1.
NMO8NI connected in series between tube 0 and ground
5. It is connected to the connection point of N16. NMO8N15
is conduction-controlled by the output of the input circuit 11, and the NMO
The conduction of 8N 16 is controlled by the output of the inverter circuit f8.

In such a configuration, the basic operation LL is similar to that shown in FIG. is accelerating.

That is, when the input signal rises from low level to high level, NMO8N5 becomes conductive and the complementary signal φ
At the same time as begins to fall, NMO8N13 becomes conductive and NMO8N14 becomes semi-conductive. This results in
From the square load (not shown) □ Br via NMO8N 13
A current flows to the base of O3, BrO3 becomes conductive, and the falling speed of the complementary signal φ is accelerated.

Further, when the input signal falls from high level to low level, NMO8N7 becomes conductive.

The complementary signal φ begins to fall, and NMO8N15 becomes conductive and NMO8N16 becomes non-conductive.

As a result, B T Q Fi becomes conductive in the same manner as described above, and the falling speed 1σ of the phase i+fi signal φ is increased.

Therefore, by having this configuration, the fifth
In addition to being able to obtain the same effect as the complementary signal output circuit shown in the figure, it is also possible to sharpen the rising and falling waveforms of the complementary signals φ and φ even under high loads. can.

FIG. 8 is a circuit diagram showing the configuration of a complementary signal output circuit according to still another embodiment of the invention. The feature of this actual example is that in the complementary signal output circuit shown in FIG.
This is because NMO8N17 whose conduction is controlled by an input signal is inserted between N5 and ground.

When the input signal falls from high level to low level,
BrO3 becomes conductive due to the high level output of the input circuit 11, whereas NMO8N5 becomes non-conductive after a delay time of one inverter circuit I8 for the output of the input circuit 11. For this reason, -temporally BrO3 and NMO8
N5 becomes conductive at the same time. Therefore, when the input signal falls from high level to low level, BrO3
NMO8N17 is brought into a non-conductive state before becoming conductive to prevent a through current.

Incidentally, in the above embodiment, the impark circuit is P f
It is not limited to the 0MO8 configuration consisting of vf OS and NMO8, for example, NMO8 and a resistor or NMO
It can also be configured with only 8. Of course, even with such a configuration, similar effects can be obtained. Therefore, the present invention is not limited to the above-mentioned actual rod example, but can be implemented in other embodiments by making appropriate design changes.

[Effects of the Invention] As explained above, according to the present invention, the transistor connected between the output terminal of the inverting circuit of the even stage [1] and rFlm and the output terminal of the inverting circuit of the odd stage [1] and the power supply Since the switching operation of one or both of the complementary signals is supplemented by one or both of the transistors connected between the two transistors, the switching time for each complementary signal input signal can be easily You will be able to do 4 things to the same extent with the configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a complementary signal output circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing a physical configuration of a complementary IA output circuit based on FIG. 1, 4, 5, 7, and 8 are circuit diagrams showing the configuration of complementary signal output circuits according to other embodiments of the present invention, and FIG. 6 is the Aiura signal output horn circuit shown in FIG. 5. 9 is a diagram showing one configuration of a conventional complementary signal output circuit, and FIG. 10 is a waveform diagram of the complementary signal output circuit shown in FIG. 9. II~110...Inverter circuit

Claims (1)

[Claims] The input signal is received by the first stage of inverting circuits among multiple inverting circuits connected in series, and a complementary signal in phase with the input signal is applied to the output terminal of the even-numbered stage of inverting circuits, and the output of the odd-numbered stage of inverting circuits is a complementary signal output circuit that provides a complementary signal in phase opposite to the input signal at its terminal, and a transistor whose conduction is controlled by a signal in phase with the input signal and connected between the output terminal of the even-numbered stage inverting circuit and the power supply; and/or a complementary signal output circuit comprising a transistor whose conduction is controlled by a signal having a phase opposite to that of the input signal and which is connected between an output terminal of the odd-numbered stage inverting circuit and a power supply.