JPH0181796U - - Google Patents
Info
- Publication number
- JPH0181796U JPH0181796U JP1987178688U JP17868887U JPH0181796U JP H0181796 U JPH0181796 U JP H0181796U JP 1987178688 U JP1987178688 U JP 1987178688U JP 17868887 U JP17868887 U JP 17868887U JP H0181796 U JPH0181796 U JP H0181796U
- Authority
- JP
- Japan
- Prior art keywords
- read
- memory
- bit
- input
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
図は本案の概念を示すブロツク図である。
Claims (1)
- 読み出し専用メモリ（ＲＯＭ）１と読み書きメ
モリ（ＲＡＭ）２のそれぞれの同位のデータ端子
同志を結ぶデータ線３に各ビツト毎に入力用の手
動スイツチ４と表示用発光ダイオード５を設け、
また同位のアドレス端子同志を結ぶアドレス線６
に各ビツト毎に入力用の手動スイツチ７を設けて
成る読み出し専用メモリ書き込み器。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178688U JPH0181796U (ja) | 1987-11-24 | 1987-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178688U JPH0181796U (ja) | 1987-11-24 | 1987-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0181796U true JPH0181796U (ja) | 1989-05-31 |
Family
ID=31470296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987178688U Pending JPH0181796U (ja) | 1987-11-24 | 1987-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0181796U (ja) |
-
1987
- 1987-11-24 JP JP1987178688U patent/JPH0181796U/ja active Pending
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