JPH0181797U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing an embodiment of the memory 10 cell 12 shown in FIG. 1, and FIG.
4 is a diagram showing an example of the memory 1 fixed cell 14 shown in FIG. 1, and FIG. 5 is an example of the memory 0 fixed cell 15 shown in FIG. 1. 6 is a diagram showing an embodiment of the address decoder 2 shown in FIG. 1, FIG. 7 is a block diagram showing a conventional read-only memory device, and FIG. 8 is a memory shown in FIG. 7. FIG. 9 is a diagram showing an embodiment of the memory 0 cell 5 shown in FIG. 7. In the figure, 1 is a memory address line, 2 is an address decoder, 3 is a word line, 6 is a bit line, and 7 is a memory address line.
1 is a pull-up circuit, 8 is a data driver, 11 is a memory data switching signal line, 12 is a memory 10 cell, 13 is a memory 01 cell, 14 is a memory 1 fixed cell, and 15 is a memory 0 fixed cell. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] In a read-only memory device composed of MOS type transistors, an address decoder that decodes a memory address, a word line that is an output from the address decoder, and a logical value 1 data stored in the read-only memory are converted into a logical value. 0 data, and a memory data switching signal line that switches logical value 0 data to logical value 1 data, and the desired word line, and becomes logical value 1 data when the memory data switching signal line is insignificant, The memory data switching signal line is selected by the 10 memory cells which have a logic value of 0 data when it is significant, and the required word line, and when the memory data switching signal line is non-significant, it becomes a logic value of 0 data, and when it is significant, it has a logic value of 1.
A memory 01 cell that becomes data, a memory 1 fixed cell that is selected by the required word line and becomes logical value 1 data regardless of the state of the memory data switching signal line, and a memory 1 fixed cell that is selected by the required word line and a memory 0 fixed cell that has logical value 0 data regardless of the state of the memory switching signal line;
the memory 10 cell and the memory 01 cell,
and a plurality of bit lines to which bits of the same weight are connected with the outputs from the memory 1 fixed cell and the memory 0 fixed cell, a plurality of pull-up circuits that pull up the bit lines, and a plurality of pull-up circuits that pull up the data on the bit lines. A read-only memory device characterized by comprising a data driver that outputs data to the outside of the read-only memory.