JPH01817A - logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a logic circuit that is configured with a small number of active elements and is capable of ternary versus binary logic operation, uses normal type transistors, and is similar to the case where RHET is used. The purpose of the present invention is to provide a logic circuit which uses an extremely small number of elements and is therefore capable of high-speed ternary versus binary logic operation, and which includes a first power supply and a second power supply having a lower voltage than the first power supply. 2 power supply and 1. an output terminal, a load means provided between the first power source and the output terminal, and first and second field effect transistors provided in series between the output terminal and the second power source; A predetermined constant voltage terminal connected to the gate of the first field effect transistor connected to the output terminal, and an input terminal (VIN) connected to the gate 1 of the second field effect transistor. The second field effect transistor connected to the second power supply is configured to have a junction having rectifying characteristics between the gate and the source.

[Industrial application field]

The present invention relates to a logic circuit configured with a small number of active elements and capable of ternary versus binary logic operation.

[Conventional technology]

Currently, most of the logic circuits that are widely used are related to binary logic of "0" and "1", and basic gates include inverters, NOR (NOR) circuits, and NAND (NA
(ND) circuits are used, and a desired function is realized by combining a large number of such gates.

FIG. 11 is a circuit diagram of a main part of a conventional general exclusive NOR circuit.

In the figure, A and B indicate input terminals, C indicates output terminal, and vno indicates positive power supply voltage.

As can be seen from the figure, this circuit requires eight field effect transistors as active elements.

By the way, in order to realize a high-speed logic circuit, the basic gates must be made high-speed, or the basic gates must be made multi-functional.
It is necessary to reduce their number.

In recent years, resonant tunneling and
transistor (resonant-tunneling)
transistor: RHET) has been developed.

FIG. 12 is a main part circuit diagram showing an exclusive NOR circuit using RHET, and the same symbols as those used in FIG. 11 indicate the same parts or have the same meanings.

The gate voltage vs. drain current in RHET exhibits an N-shaped characteristic, that is, a negative differential characteristic, and by utilizing this characteristic, various circuits can be constructed. , only one RHET
It is one of the expected high-speed logic circuits.
47-350J).

[Problem to be solved by the invention]

Logic circuits using RHETs, such as the one shown in Figure 12, are very valuable because they use a small number of elements and are fast, but at present it is not possible to manufacture RHETs. Therefore, it is difficult to integrate the circuit into an integrated circuit.

The present invention uses a normal type transistor, and furthermore, R
Similar to the case using HET, the present invention aims to provide a logic circuit that uses an extremely small number of elements and is therefore capable of high-speed ternary versus binary logic operation.

[Means to solve the problem]

The present invention is based on the use of a field effect transistor having rectification between the gate and source, such as a Schottky gate or a pn junction gate, as an active element. That is, the field effect transistor is configured to have a dual gate, or two field effect transistors are connected in series to form a four-terminal circuit with negative mutual conductance.

FIG. 1 shows a circuit diagram of a main part of a dual gate field effect transistor used in the present invention.

The field effect transistor targeted here is a high electron mobility transistor.
n mobility transi s to
r: HEMT).

In the figure, S indicates a source, D indicates a drain, G1 indicates a first gate, and G2 indicates a second gate.

FIG. 2 is a diagram for explaining the static characteristics of the dual gate HEMT shown in FIG.

In the figure, the horizontal axis shows the voltage ■Gl applied to the first gate G1.
, the drain-source current ros is plotted on the vertical axis, and the voltage VG applied to the second gate G2 is
2 as a parameter, which is OCV), 0.2
(V), 0.4 (V), and 0°6 [■]. In addition, the drain-source voltage at this time is ■. , was set to 1 [v].

Figure 3 shows the dual gate (also seen in Figure 1) (
This is a diagram for explaining the static characteristics of EMT, and the same symbols as those used in FIG. 2 indicate the same parts or have the same meaning.

This data was obtained by taking the voltage VG2 applied to the second gate (G2) on the horizontal axis and using the voltage VC+ applied to the first gate 0.1 as a parameter, contrary to the case in Figure 2. Yes, that voltage is V. , are O(V) , 0.2 (V), 0.4 (V) , 0 as in the case of Fig. 2.
．． 6 (V).

As is clear from FIGS. 2 and 3, the second gate G2
Increasing the forward voltage at gate G1 reduces the effective gate voltage at gate G1 due to the forward current and the presence of source resistance, resulting in a negative transconductance as seen in Figure 3. It is something that appears.

As is clear from Fig. 3, this dual gate HE
Since the MT has a switching characteristic of being turned on only in response to a constant gate voltage, by utilizing this characteristic, a logic circuit can be constructed with a small number of elements.

When a dual-gate HEMT (as seen in FIG. 1) is uniformly excited, it is represented as two HEMTs connected in series as shown in FIG. Even if it is not, it can be configured by using two ordinary field effect transistors. Of course,
In that case as well, the gate needs to have rectifying properties, such as a Schottky gate or a pn junction gate.

Therefore, in the logic circuit according to the present invention, a first power source, a second power source having a lower voltage than the first power source,
an output terminal, a load means provided between the first power source and the output terminal, and first and second field effect transistors provided in series between the output terminal and the second power source;
a predetermined constant voltage terminal connected to the gate of the first field effect transistor connected to the output terminal; and an input terminal connected to the gate of the second field effect transistor (
The second field effect transistor connected to the second power supply is configured to have a junction having rectifying characteristics between the gate and the source.

[Effect]

By adopting the above method, a basic gate capable of ternary versus binary logic operation can be easily obtained by using only one or two ordinary field effect transistors, and therefore an exclusive NOR gate can be easily obtained. Circuits can also be constructed with the same number of active elements, and because the number of active elements is small, the circuit can be made faster, and since the active elements can be ordinary ones, manufacturing is easy. , it is possible to integrate it into an integrated circuit without any difficulty.

〔Example〕

FIG. 5 shows a circuit diagram of a main part of a logic circuit which is a basic gate of an embodiment of the present invention, and the same symbols as those used in FIGS. 1, 11 and 12 indicate the same parts. or have the same meaning.

In the figure, VIN represents the input voltage, VREF represents the reference voltage, and VOLI represents the output voltage.

FIG. 6 shows a circuit diagram of a main part of a logic circuit which is a basic gate of another embodiment, and the same symbols as those used in FIG. 5 indicate the same parts or have the same meanings.

In the figure, Ql and Q2 are normal HEMTs.

Rs represents the source resistance, Ic represents the gate current, and VCS represents the gate-source voltage.

This embodiment is constructed using two conventional HEMTs, whereas the active elements in the embodiment shown in FIG. 5 are dual gate HEMTs.

Next, the specific operation of the embodiment will be explained with reference to FIG. 6 for easy understanding.

For example, the positive side power supply voltage van is 1.5 (V), and the reference voltage V RtF is 0.5 (V). 4 f:V), and the input voltage VIN is varied in the range of O(V) to 1.5 (V).

Now, when the input voltage VIN is 0 (V) (7), HEM
Since TQl is in the off state, the output voltage ■out is at a high level. Next, the input voltage VIN is increased so that it is the threshold voltage of HEMT-Ql (for example, 0.
When the voltage exceeds 1 (V)), HEMT/Ql is turned on. Therefore, the source voltage of HEMT-Q 2 to which the reference voltage V REF is applied is 0 [V]
As a result, the gate-source voltage VGS
exceeds the threshold voltage, so it is in the on state. As a result, the output voltage V. LIT goes low. If the input voltage VIN is further increased and exceeds the on-voltage of the Schottky junction generated between the gate electrode and channel region of the HEMT-Ql, the gate junction of the HEMT-Ql will turn on, and the voltage will be switched from the gate to the source. Gate current ■ flows toward. In general, a field effect transistor parasitically has a source resistance R8, so when the gate current 1c flows as described above, a voltage drop occurs there, and the source potential of HEMT-Q2 rises, turning it into an off state. . As a result, the output voltage ■. LIT transitions to high level again.

In this way, in the logic circuit of the present invention, the input voltage V
Corresponding to IN changing from low level through intermediate level to high level, the output voltage ■. Ut changes from high level to low level, then back to high level again.

In order to guarantee this kind of operation, the reference voltage V
The value of IItF is (1) Best gate-source voltage of HEMT-Q2 when the gate junction of HEMT-Ql is off.
(2) HEM such that is greater than its threshold voltage
HEMT- when the gate junction of T-Ql is on
It is necessary to set the gate-source voltage VG*t of Q2 to be smaller than its threshold voltage.

FIG. 7 shows input voltage VIN versus output voltage V for the embodiments shown in FIGS. 5 and 6. , JT.

In the figure, the horizontal axis represents the input voltage VIN, and the vertical axis represents the output voltage V.

LJ? are taken respectively. Note that the reference voltage vRtF when this data was obtained was 0.4 (V).

As is clear from FIG. 7, the logic circuits shown in FIGS. 5 and 6 have a binary output voltage V for a ternary input voltage VIN. Ua is output, therefore, ternary versus binary logic operation is possible, and the relationship is summarized in the following table.

Here, "L" indicates a low level, FI' indicates a high level, and "IIM" indicates a level intermediate between the L" level and the "H" level. Note that the reference voltage VRE in this case is preferably set near the 1ltLl threshold at which the input voltage VIN changes from the "L" level to the "M" level.
In the experiment that obtained the above data, the above-mentioned 0, 4 (Vl
was equivalent to that.

FIG. 8 shows a main part circuit diagram of an embodiment of an exclusive NOR circuit constructed using the basic gate shown in FIG. 5, and FIGS. 5 and 6, and FIGS. The same symbols used in the above shall indicate the same parts or have the same meaning.

The logical operation in this embodiment, ie, the relationship between input and output, is summarized in the following table.

According to this embodiment, the same function as that of the circuit described with respect to FIGS.
This is realized using multiple HEMTs.

FIG. 9 is a cutaway side view of the main part showing the specific structure when the basic gate is configured with HEMT, and FIG. 10 is a main part circuit diagram equivalently showing the basic gate shown in FIG. 9. The same symbols as those used in FIGS. 1, 5, 6, and 8 indicate the same parts or have the same meaning.

In the figure, ■ is a semi-insulating GaAs substrate, 21J
i-type G a A, s channel layer, 3 is n-type A l!
Ga As electron supply layer, 4 is n-type Ga i',
4i −, 'i > Kuku! -Layer 1. , 'i is an insulating isolation region, 6 is a drain electrode, 6A is an alloying region, 7 is a source/drain electrode, and 78 is a combination.

8 is a source electrode, 8A is an alloyed region, 9 is a gate electrode, 10 is a two-dimensional electron gas layer, Q10 is a load side transistor, and QD is a drive side transistor. Note that the drive side transistor QD is an enhancement type, and the load side transistor QL is a depletion type, and although they are called transistors, they of course play the role of a resistor.

To manufacture the semiconductor device shown in the figure, the objective can be easily achieved by applying a technology that is completely different from the technology used to manufacture general HEMTs, except that it requires the formation of dual gates. In addition, there is no technical difficulty in forming dual gates, just by changing the mask pattern.

〔Effect of the invention〕

In the logic circuit according to the present invention, a field effect transistor having rectification characteristics between the gate and the source is used as an active element, and a four-terminal circuit in which two terminals are gates and has negative mutual conductance is used. I am trying to configure it with .

With such a configuration, a basic gate capable of ternary versus binary logic operation can be easily obtained by using only one or two ordinary field effect transistors, and therefore an exclusive gate can be obtained. NOR circuits can also be constructed with the same number of active elements, and because the number of active elements is small, the circuit can be made faster, and since the active elements can be ordinary ones, it is easy to manufacture. Therefore, it is possible to integrate it into an integrated circuit without the difficulties encountered when using RHET.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the main part of the dual-gate field effect transistor used in the present invention, and Figures 2 and 3 are lines for explaining the static characteristics of the dual-gate field-effect transistor shown in Figure 1. 4 is an equivalent circuit diagram of a dual gate 1-HEMT, FIG. 5 is a circuit diagram of a main part of a logic circuit which is a basic gate of one embodiment of the present invention, and FIG. 6 is a circuit diagram of another embodiment of the present invention. Figure 7 is a circuit diagram of the main part of a logic circuit which is a basic gate, and shows the input voltage V vs. output voltage V of the embodiment shown in Figures 5 and 6.
A diagram explaining the relationship between OLITs, Figure 8 is a circuit diagram of the main part of an exclusive NOR circuit constructed using the basic gates shown in Figure 5, and Figure 9 is a diagram when the basic gates are constructed with HEMTs. Main part cutaway side view showing the specific structure of
Figure 0 is an equivalent circuit diagram of the basic gate shown in Figure 9, and Figures 11 and 12 are circuit diagrams of the exclusive NOR circuit according to the prior art. . In the figure, S is the source, D is the drain, G1 is the first gate, G2 is the second gate, VIN is the input voltage, and V RE
F is the reference voltage, ■. 0. indicate the output voltage, respectively. Figure 1 vGl Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 IN Diagram showing the relationship between input voltage and output voltage Figure 7 Main part circuit diagram of one embodiment Figure 8 Figure 10 General Main part circuit diagram of e'AH exclusive Noah circuit Figure 11 Figure 12

Claims (1)

[Claims] 1. A first power source (V_D_D), and a second power source (V_S) having a lower voltage than the first power source.
_S), an output terminal (V_O_U_T), a load means provided between the first power source and the output terminal, and a first and second power source provided in series between the output terminal and the second power source. a field effect transistor; a predetermined constant voltage terminal connected to the gate of the first field effect transistor connected to the output terminal; and an input terminal connected to the gate of the second field effect transistor. (V_I_N), wherein the second field effect transistor connected to the second power supply has a junction having rectifying characteristics between the gate and the source. 2. The voltage value of the constant voltage terminal is such that when the second field effect transistor is on and its gate junction is off, the gate-source voltage of the first field effect transistor is is greater than the threshold voltage of the first field effect transistor, and when the gate junction of the second field effect transistor is in an on state, the gate-source voltage of the first field effect transistor is higher than the threshold voltage of the first field effect transistor. 2. The logic circuit according to claim 1, wherein the voltage is lower than the threshold voltage of one field effect transistor. 3. The gate junction of the second field effect transistor is connected to the input terminal from a level where the gate-source voltage of the second field effect transistor is lower than the threshold voltage of the second field effect transistor. 2. The logic circuit according to claim 1, wherein an input voltage is applied that varies within a range of a level higher than a voltage for turning on.