JPH0183340U - - Google Patents
Info
- Publication number
- JPH0183340U JPH0183340U JP1987179155U JP17915587U JPH0183340U JP H0183340 U JPH0183340 U JP H0183340U JP 1987179155 U JP1987179155 U JP 1987179155U JP 17915587 U JP17915587 U JP 17915587U JP H0183340 U JPH0183340 U JP H0183340U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- layer wiring
- upper layer
- lower layer
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 2
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案の実施例を示す半導体集積回路
の断面図、及び第２図は従来の半導体集積回路の
一構成例を示す断面図である。
１１……半導体基板、１３……酸化膜、１５…
…下層配線パターン、１６……上層配線パターン
、１７……絶縁膜。
FIG. 1 is a sectional view of a semiconductor integrated circuit showing an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of the configuration of a conventional semiconductor integrated circuit. 11... Semiconductor substrate, 13... Oxide film, 15...
...Lower layer wiring pattern, 16... Upper layer wiring pattern, 17... Insulating film.
Claims (1)
ぞれ形成された上層配線パターンと下層配線パタ
ーンとを有し、前記上層配線パターンと下層配線
パターンとが並列に接続された多層配線構造の半
導体集積回路において、 前記下層配線パターンの一部に前記上層配線パ
ターンの一部を直接に重畳したことを特徴とする
半導体集積回路。[Claims for Utility Model Registration] An upper layer wiring pattern and a lower layer wiring pattern are formed above and below a semiconductor substrate through an insulating film, and the upper layer wiring pattern and the lower layer wiring pattern are connected in parallel. 1. A semiconductor integrated circuit having a multilayer wiring structure, characterized in that a part of the upper wiring pattern is directly superimposed on a part of the lower wiring pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987179155U JPH0183340U (en) | 1987-11-25 | 1987-11-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987179155U JPH0183340U (en) | 1987-11-25 | 1987-11-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0183340U true JPH0183340U (en) | 1989-06-02 |
Family
ID=31470735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987179155U Pending JPH0183340U (en) | 1987-11-25 | 1987-11-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0183340U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870002A (en) * | 1994-08-29 | 1996-03-12 | Nec Corp | Semiconductor device and manufacturing method thereof |
-
1987
- 1987-11-25 JP JP1987179155U patent/JPH0183340U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870002A (en) * | 1994-08-29 | 1996-03-12 | Nec Corp | Semiconductor device and manufacturing method thereof |