JPH0183347U - - Google Patents
Info
- Publication number
- JPH0183347U JPH0183347U JP1987178412U JP17841287U JPH0183347U JP H0183347 U JPH0183347 U JP H0183347U JP 1987178412 U JP1987178412 U JP 1987178412U JP 17841287 U JP17841287 U JP 17841287U JP H0183347 U JPH0183347 U JP H0183347U
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead
- terminal
- pin
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の実施例を示すＩＣパツケージ
の側面図、第２図は本考案のスルーホールの構成
を示す図、第３図は本考案の半導体チツプとイン
ナーリードとの接続状態を示す平面図、第４図は
本考案のＩＣパツケージの半導体チツプ部とイン
ナーリードとの接続状態を示す断面図、第５図は
従来のＤＩＰの斜視図、第６図は従来のＦＰＰの
斜視図である。
１０…ＩＣパツケージ、１１…ピン、１２…第
１のリード、１３…絶縁物、１４…第２のリード
、１５…アイランド、１６…半導体チツプ、１７
…パツド、１８…ワイヤ、１９…封止樹脂、２０
…スルホール、２１…第１の端子、２２…第２の
端子。
Fig. 1 is a side view of an IC package showing an embodiment of the invention, Fig. 2 is a diagram showing the configuration of the through-hole of the invention, and Fig. 3 is a diagram showing the state of connection between the semiconductor chip and inner leads of the invention. FIG. 4 is a plan view, FIG. 4 is a sectional view showing the connection state between the semiconductor chip part and the inner lead of the IC package of the present invention, FIG. 5 is a perspective view of a conventional DIP, and FIG. 6 is a perspective view of a conventional FPP. be. DESCRIPTION OF SYMBOLS 10... IC package, 11... Pin, 12... First lead, 13... Insulator, 14... Second lead, 15... Island, 16... Semiconductor chip, 17
... Pad, 18... Wire, 19... Sealing resin, 20
...through hole, 21...first terminal, 22...second terminal.
Claims (1)
、絶縁体を挟んで第１のリードと第２のリードが
一体に形成されるピンを具備するようにしたこと
を特徴とするＩＣパツケージ。 (2) 第１の端子と、第２の端子が形成される単
一のスルーホールを具備する基板を設け、前記第
１の端子を前記第１のリードを、前記第２の端子
に前記第２のリードを接続するようにしたことを
特徴とする実用新案登録請求の範囲第１項記載の
ＩＣパツケージ。[Claims for Utility Model Registration] (1) A pin-insertion type IC package characterized by having a pin that integrally forms the first lead and the second lead with an insulator in between. IC package. (2) providing a substrate having a single through hole in which a first terminal and a second terminal are formed; The IC package according to claim 1 of the utility model registration claim, characterized in that two leads are connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178412U JPH0183347U (en) | 1987-11-25 | 1987-11-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178412U JPH0183347U (en) | 1987-11-25 | 1987-11-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0183347U true JPH0183347U (en) | 1989-06-02 |
Family
ID=31470033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987178412U Pending JPH0183347U (en) | 1987-11-25 | 1987-11-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0183347U (en) |
-
1987
- 1987-11-25 JP JP1987178412U patent/JPH0183347U/ja active Pending
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