JPH01835A - frame synchronizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital communication system using a signal train in which specific codes are inserted at regular intervals, and in particular to a frame synchronization system drop insertion (Drop Insertion).
ion ) functions.

[Conventional technology]

Conventionally, the auxiliary data signal included in this type of signal has been transferred in and out using a drop insertion function within a repeater.

FIG. 3 is a block diagram showing an example of a circuit configuration of a drop insertion function used in a conventional repeater.

In the figure, 21 is a serial/parallel conversion circuit, 22 is a synchronous circuit, 23 is a drop insertion circuit, 24 is a parallel/serial conversion circuit, and 25 is an N frequency divider circuit. And 2
6a, 26b indicate data signals, 27a, 27b,
27e is a parallel signal, 28 is a control signal, 29 is a clock signal, and 30.31 is an N-phase clock signal.

Now, an N-phase clock signal 30 is generated from the clock signal 29 by the N-frequency divider circuit 25, and the data signal 26a inputted from the transmission line is converted to the serial/parallel converter circuit 21 by this N-phase clock signal 30. The signal is divided into N parallel signals 27a and sent to the synchronization circuit 22. This synchronization circuit 22 detects the frame signal of the input data signal 26m and applies feedback using a control signal 28 so that the frame position is constant. The output of the synchronization circuit 22 is output from the drop insertion circuit 23.
After extraction and insertion of the auxiliary data signal are performed, the parallel/serial conversion circuit 24 converts the auxiliary data signal into a data signal 26b, which is a serial signal, and becomes a signal to be transmitted to the transmission line. At this time, the parallel/serial conversion circuit 24 performs interleaving using the N-phase clock signal 31 generated by the N frequency divider circuit 25, and performs timing using the clock signal 29.

[Problem that the invention seeks to solve]

In the parallel-to-serial conversion circuit 24 in the conventional drop insertion function described above, the N-phase clock signal 31 generated by the N-frequency divider circuit 25 is used to interleave and timing is performed using the clock signal. N
There is a problem in that interleaving is very difficult due to a slight delay in the phase clock signal 31 or a shift in duty.

[Means for solving problems]

The frame synchronization method of the present invention is a digital communication method that uses a signal train in which specific signals are inserted at regular intervals, and includes a serial/parallel conversion circuit that converts an input data signal into a parallel signal, and a serial/parallel conversion circuit that converts an input data signal into a parallel signal. A parallel/serial conversion circuit that converts a parallel signal from a circuit into a serial signal, and first and second N frequency divider circuits connected to the serial/parallel conversion circuit and the parallel/serial conversion circuit, respectively. It was made so that it would become so.

Further, a frame synchronization system according to another aspect of the present invention is such that a memory circuit is provided in the preceding stage of the parallel/serial conversion circuit in the above-mentioned system.

[Effect]

In the present invention, an input data signal is converted into N parallel signals by a serial/parallel conversion circuit using an N-phase clock signal from an N frequency divider circuit, and sent to a synchronous circuit. The frame signal of the data signal is detected and fed back using a control signal so that the frame position is constant.

Then, the output of this synchronous circuit is input to the drop insertion circuit, where the auxiliary data signal is outputted and inserted into the y, and then the parallel signal is serialized by the parallel/serial conversion circuit. be converted into Further, in another invention of the present invention, a buffer memory circuit is provided at the output of the drop insertion circuit, and the parallel signal read out from the read clock signal button generated by the N frequency divider circuit is converted from parallel to serial. Convert it to a serial signal using a circuit.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the frame synchronization method according to the present invention.

In the figure, 1 is a serial/parallel conversion circuit that converts an input data signal into a parallel signal, and 2 is this serial/parallel conversion circuit 1.
3 is a drop insertion circuit that receives the parallel signal from the synchronous circuit 2 as input, 4 is the parallel signal that is the output of this drop insertion circuit 3, i.e. , a parallel/serial conversion circuit that converts the parallel signal from the serial/parallel conversion circuit 1 into a serial signal, 5″″ and 6 are N frequency dividers connected to the serial/parallel conversion circuit 1 and the parallel/serial conversion circuit 4, respectively. It is a circuit.

And 8a, ab are data signals, 9a, 9b,
9 e is a parallel signal, 10 is a control signal supplied from the synchronous circuit 2 to the N frequency divider circuit 5゜6, 11 is a clock signal, 12a and 12b are serial signals from the N frequency divider circuit 5 and N frequency divider circuit 6, respectively.・Parallel conversion circuit 1 and parallel・
This is an N-phase clock signal supplied to the serial conversion circuit 4.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, an N-phase clock signal 12a is generated from the clock signal 11 by the N frequency divider circuit 5, and by this N-phase clock signal 121L, the input data signal 8a is converted into N parallel signals by the serial/parallel conversion circuit 1. It is converted into a signal 9a and sent to the synchronization circuit 2. The synchronization circuit 2 detects the frame signal of the input data signal 8a and feeds it back using a control signal 10 so that the frame position is constant.

The output of the synchronization circuit 2 is then input to a drop insertion circuit 3, where the auxiliary data signal is extracted and inserted.

Thereafter, the parallel signal 9C is serialized by the parallel/serial conversion circuit 4, but here, the Nil clock signal 12b for interleaving is sent to the N frequency divider circuit 6.

Then, in order to convert N parallel signals into direct current in 7 order, N
The frequency dividing circuits 5 and 6 must be synchronized, and this control is performed using a control signal 10 from the synchronization circuit 2.

FIG. 2 is a block diagram showing another embodiment of the invention.

In FIG. 2, the same reference numerals as in FIG. ). And 9'C
are parallel signals, and 13a and 13b are read clock signals supplied from the N frequency divider circuit 6 to the drop insertion circuit 3 and the memory circuit 7, respectively.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, since the operations of the parts with the same reference numerals as in FIG. 1 are completely the same as in FIG. 1, their explanations will be omitted here.

Next, there is a memory circuit γ on the output side of the drop insertion circuit 3, and a parallel signal 9 is read out from the clock signal 11 by the read clock signal 13b generated by the N frequency divider circuit 6. 'c is converted into a serial signal by the parallel/serial conversion circuit 4, but N
Since it is synchronized with the phase clock signal 12b, serial conversion can be easily performed.

〔Effect of the invention〕

As is clear from the above description, although the present invention requires somewhat more power consumption and mounting area than conventional systems of this type, it suppresses the operating speed of components (elements), which is a particular problem in high-frequency circuits, and This has the advantage that a stable circuit can be constructed and it can be easily integrated into an LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the frame synchronization method according to the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing a drop inserter conventionally used in repeaters. FIG. 2 is a block diagram illustrating an example of a circuit configuration of a function. 1...Serial/parallel conversion circuit, 4...
・Parallel/serial conversion circuit, 5, 6...N frequency divider circuit, γ...Buffer memory circuit (memory circuit).

Claims (2)

[Claims] (1) In a digital communication system that uses a signal train in which specific signals are inserted at regular intervals, a serial/parallel conversion circuit converts an input data signal into a parallel signal, and a parallel signal from this serial/parallel conversion circuit. Parallel converter to serial signal
a serial conversion circuit, a first and a second circuit connected to the serial/parallel conversion circuit and the parallel/serial conversion circuit, respectively;
A frame synchronization method characterized by comprising an N frequency divider circuit. (2) In a digital communication system that uses a signal train in which specific signals are inserted at regular intervals, a serial/parallel conversion circuit converts an input data signal into a parallel signal, and a parallel signal from this serial/parallel conversion circuit. Parallel converter to serial signal
a serial conversion circuit, a first and a second circuit connected to the serial/parallel conversion circuit and the parallel/serial conversion circuit, respectively;
A frame synchronization system comprising: an N frequency divider circuit; and a memory circuit provided before the parallel/serial conversion circuit.