JPH01850A - Continuity test path setting method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In a time-division channel device equipped with a double-buffer type time-division switch, a supervisory signal generator and a supervisory signal receiver for continuity testing, a time slot for extracting a supervisory signal is set. By setting a continuity test path at the same time as the time slot in which the monitoring signal is stored, or later than the time slot in which the monitoring signal is stored, it is possible to detect a failure that occurs in the double-buffer type time division switch.

[Industrial application field]

The present invention relates to an improvement in a continuity test path setting method in a time/minute communication path device used in a digital exchange.

In recent years, time-division channel devices of digital exchanges have been required to transmit not only telephone signals but also data signals.

Furthermore, in order to transmit high-speed data, multiple time slots may be used together, and in such cases, the so-called T S Sl (Time
5lot 5equence Integrity)
Functionality is required, and a method of configuring a time division switch into a double buffer type has been adopted as a means to achieve this.

On the other hand, in order to comprehensively check the normality of the call path setting function, the time-division channel device inputs a monitoring signal to a specific time slot and checks whether it is output to the specific time slot. It is equipped with continuity test board capability.

Even in the double buffer type time division switch described above, a continuity test method is required that can reliably detect failures.

[Conventional technology]

FIG. 6 is a diagram illustrating an example of a single buffer type time division switch, and FIG. 7 is a diagram illustrating the successive writing process in FIG. 6.

In FIG. 6 and FIG. 7, each time slot TSI to TS having a period of frame F starts from the input highway 2.
, is specified by the write address a, (=1.2, . . . , k) output from the address counter 12 in synchronization with the time slot TS, or TS. The data are sequentially stored in the data memory 11 in the first half of each time slot (T S to T S' K).

Further, the address control memory 13 stores successive addresses ar (=a, b ,...
, X) and transmits it to the data memo 1J11.

The data memory 11 is an address control memory 13.
The data D to DX stored in the area specified by the subsequent address a transmitted from TS is extracted and sent to the output highway 3 during the latter half of each time slot TSl to TSi.

For example, if the address control memory 13 stores successive address a7=1 corresponding to successive address address ac=i, and stores successive address ar=k corresponding to successive address address ac=j, then the input Data D1 input from highway 2 at time slot TS is sent to outbound highway 3 at time slot TS, and data Dk input from highway 2 at time slot TSK is sent to outbound highway 3 at time slot TSJ. sent to.

As a result, data D sent in time slot TSI is different from time slot TS in the same frame F.
is input in time slot TS,
The data D sent out in T is input in time slot TSK in the previous frame F, and
The SSI function will not be realized.

Next, FIG. 2 is a diagram showing an example of a double buffer type time division switch to which the present invention is applied, and FIG. 3 is a diagram illustrating the write/read process in FIG. 2.

In FIGS. 2 and 3, the time division switch 10 is equipped with two sets of data memories 101 and 102, and each data D1 to Dk arriving from the input highway 2 in each time slot TS1 to TS is stored in a frame F- The address counter 1 is stored in the data memory 101 in r, in the data memory i02 in the next frame F0, and again in the data memory 101 in frame F-r.
Write address a output from 03. It is stored in the area specified by .

Note that in frame F-, data D to DX stored in the previous frame F4 (not shown) are transferred from the data memory 102 to the address control memory 10.
In frame FO, the data D3 to data stored in the previous frame F-+ from the data memory 101 are extracted from the area designated by the successive address a transmitted from the data memory 101 to the address control memory 1.
04, and further in frames F and l,
The data D to DX stored in the previous frame F0 from the data memory 101 are extracted from the area specified by the subsequent address a transmitted from the address control memory 104 and sent to the output highway 3.

As described above, the data D extracted in each time slot TS to T S K of each frame F, FO, , F, is the same as that of the previous frame F7, FO, , F.
Since the data was stored in the I"351 function, the I"351 function is realized.

In this state, the pilot signal generator (PG) 5 and the pilot signal receiver (PC) are connected to the time division switch 10.
6, and the pilot signal generator 5 generates two types of patterns as the monitoring signal P (for example, a pattern consisting of 8 bits).
01010101) and pattern (10101010
)) are generated alternately every frame F, and from the input highway 2 to a specific time slot (for example, TS or TS
The pilot signal receiver 6 receives the data memory or D5 that is input to the time division switch 10 at X) and output from the time division switch 10 to the output highway 3 in a specific time slot (for example, T S + or TSJ). Then, a continuity test of the time division switch 10 is performed to check whether the monitoring signal P has the pattern as described above.

Next, FIG. 4 is a diagram showing an example of a failure occurring in a double buffer type time division switch, and FIG. 5 is a diagram illustrating the write/read process in FIG. 4.

In FIG. 4, the storage function of data D to Dk in the data memory 101 has failed, and data D to Dk should normally be stored in frames F-+, F, and I, but not in frame F0. Frame F, even though data D3 to DX should have been extracted without any problem. Data D to Dk are also stored in ζ
There is.

As a result, in frame F0, data memory 10
1 performs a single buffer type operation in which data D+ to Dk are stored in the first half period of each time slot TSL to TSK, and data D1 to D are extracted in the second half period.

In this state, the monitoring signal P generated by the pilot signal generator 5 is input to the time division switch 10 from the human highway 2 at time slot TSK, and is input from the time division switch 10 to the output highway 3 at time slot TSJ.
Suppose that the pilot signal receiver 6 monitors the data D output to the data memory 10 in the frame F0 and in the frame F-,
i t:,'One butter of the stored monitoring signal P
(01010101)), and in the next frame F+1, data memory 10 is received in frame F0.
The other pattern of the monitoring signal P stored in 2 [for example (
As a result of receiving 10101010)), the supervisory signal P is received normally, and the hour/minute H switch 10 is determined to be normal as a result of the continuity test, and the occurring fault is not detected.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional continuity test path setting method, there is a risk of failing to detect a failure that occurs in a double buffer type time division switch. FIG. 2 is a diagram showing the principle of the invention.

In FIG. 1, 100 and 200 are both data memories, 300 is a double buffer type time division switch, and 40 is a double buffer type time division switch.
0 is a supervisory signal generator that generates a supervisory signal P for continuity testing, and 500 is a supervisory signal receiver that detects the supervisory signal P@.

Further, F is a frame, TS, and TS are time slots.

600 is address generation means provided in the double buffer type time division switch 300 according to the present invention.

[Effect]

The address generating means 600 operates at a time slot 1 for extracting the monitoring signal P from the double buffer type time division switch 300.
-TS, at the same time as the time slot TS in which the monitoring signal P is stored in the double-buffered time division switch 300, or at a later time, so that the data memory 100.
The writing timing and reading timing to 200 are set.

Focusing on the values of W and r, the address generation means 600
acts so as to satisfy the condition r≧W.

As a result, if the double buffer type time division switch 300
A failure occurs in one of the data memories (for example, 100).
In frame F, which performs the same operation as the single-buffer type, the monitoring signal P stored in time slot TS is transmitted to time slot TS in the same frame F.
data memory of the other side.
(for example, 200), when extracting the monitoring signal P stored in the immediately preceding frame Failures can be detected.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 4 and 5.

In FIG. 4, address control memory 104 functions as address generation means 600.

In FIG. 4, the above-mentioned failure occurs and the frame F
It is assumed that data DI to Dk are also stored in , and a single buffer type operation is performed.

In this state, if the monitoring signal P generated by the pilot signal generator 5 is input from the human highway 2 to the time division switch 10 at time slot TS+ (i.e., W=1), the pilot signal receiver 6 Since the time slot (TS) for monitoring the monitoring signal P extracted from the switch 10 to the output highway 3 satisfies the condition r≧W, it is determined to be an arbitrary time slot (for example, TS+) among the time slots TS1 to TSK.

In time slot TSI, address counter 10
3 inputs the address read address ac=i to the address control memory 104.

Therefore, by setting the successive address ar-1 in the area specified by the successive address address ac=i of the address control memory 104, the monitoring signal P input to the time slot TS can be extracted at the time slot TSI. I can do it.

As a result, the pilot signal receiver 6 receives the time slot T.
In frame F0, the monitoring signal P received at SI is one of the patterns stored in data memory 101 in time slot TS within the same frame F0.
For example (10101010)) and the next frame F
01 as well, data memory 10 in frame F0
Since it is the same pattern (10101010) stored in 2, the monitoring signal P received by the pilot signal receiver 6
is always only one pattern (101010] 0),
The other pattern (01010101) cannot be received.

As a result, the pilot signal receiver 6 receives the time division signal
Inch 10 cannot normally store and extract the monitoring signal P generated by pilot signal generator 5, and it is determined that a failure has occurred.

As is clear from the above description, according to this embodiment, the monitoring signal P generated by the pilot signal generator 5 is stored in the time division switch 10 from the human highway 2 in the time slot TS, and By extracting the signal from the division switch 10 and monitoring it with the pilot signal receiver 6, a failure occurring in the time division switch 10 can be detected.

Note that the above explanation using FIGS. 4 and 5 is only one embodiment of the present invention, and for example, the input time slot TSw and output time slot TS of the supervisory signal P are respectively the time slot TS , and time slot TSI, and any time slot that satisfies the condition r≧W can be freely selected from time slots TS to TSK.

〔Effect of the invention〕

As described above, according to the present invention, when a failure occurs in the double-buffer type time-division switch used in the time-division channel device and one of the data memories operates in the same manner as a single-buffer type, continuity is maintained. As a result of the test, it was determined that there was an abnormality,
Failures can be detected.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating an example of a double buffer type time division switch to which the present invention is applied, and FIG. 3 is a diagram illustrating the write/read process in FIG. 2. Fig. 4 is a diagram showing an example of a failure occurring in a double-buffer type time-division switch, Fig. 5 is a diagram illustrating the write/read process in Fig. 4, and Fig. 6 is an example of a single-buffer type time-division switch. The figure shown in FIG. 7 is a diagram illustrating the write/read process in FIG. 6.

Claims (1)

Claims: Two sets of data memories (100, 200) store time-division multiplexed data alternately in frame (F) units, and one data memory (100, 200) stores the data. A double buffer type time division switch (300) for time division multiplexing and extracting stored data from the other data memory (200, 100), and a monitoring signal (P) for a continuity test are generated. A supervisory signal generator (4
00) and the double buffer type time division switch (30
a supervisory signal receiver (500) that receives the supervisory signal (P) extracted from
), a time slot (TS_) for extracting the monitoring signal (P).
r) address generation for setting the writing timing and reading timing to the data memory (100, 200) so that the timing is the same as or later than the time slot (TS_w) in which the monitoring signal (P) is stored; A continuity test path setting method characterized by providing means (600).