JPH0186235U - - Google Patents
Info
- Publication number
- JPH0186235U JPH0186235U JP18326287U JP18326287U JPH0186235U JP H0186235 U JPH0186235 U JP H0186235U JP 18326287 U JP18326287 U JP 18326287U JP 18326287 U JP18326287 U JP 18326287U JP H0186235 U JPH0186235 U JP H0186235U
- Authority
- JP
- Japan
- Prior art keywords
- etching
- etching depth
- mesa groove
- shallow
- deep
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 claims 3
- 230000002093 peripheral effect Effects 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Description
第１Ａ図、第１Ｂ図、第１Ｃ図は、本考案の一
実施例を示すｐｎ接合ダイオードのメサ溝の形成
工程を示す断面図である。第２Ａ図、第２Ｂ図、
第２Ｃ図は、従来ｐｎ接合ダイオードのメサ溝の
形成工程を示す断面図である。
図において、１はｎ型シリコン基板、２はｐ型
拡散部、３は酸化膜、１１はメサ溝、１２はグラ
シベーシヨン膜を示す。図中、同一符号は同一ま
たは相当する部分を示す。
FIGS. 1A, 1B, and 1C are cross-sectional views showing the process of forming a mesa groove of a pn junction diode according to an embodiment of the present invention. Figure 2A, Figure 2B,
FIG. 2C is a cross-sectional view showing a process of forming a mesa groove of a conventional pn junction diode. In the figure, 1 is an n-type silicon substrate, 2 is a p-type diffusion part, 3 is an oxide film, 11 is a mesa groove, and 12 is a gracibation film. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
央領域のエツチング深さが深くなるようにエツチ
ングして形成されたメサ溝の壁面上に、保護膜を
形成したことを特徴とする、半導体装置。 A semiconductor device characterized in that a protective film is formed on the wall surface of a mesa groove formed by etching so that the etching depth in the peripheral region is shallow and the etching depth in the central region is deep.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18326287U JPH0186235U (en) | 1987-11-30 | 1987-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18326287U JPH0186235U (en) | 1987-11-30 | 1987-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0186235U true JPH0186235U (en) | 1989-06-07 |
Family
ID=31474691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18326287U Pending JPH0186235U (en) | 1987-11-30 | 1987-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0186235U (en) |
-
1987
- 1987-11-30 JP JP18326287U patent/JPH0186235U/ja active Pending
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