JPH0186367U - - Google Patents
Info
- Publication number
- JPH0186367U JPH0186367U JP17997987U JP17997987U JPH0186367U JP H0186367 U JPH0186367 U JP H0186367U JP 17997987 U JP17997987 U JP 17997987U JP 17997987 U JP17997987 U JP 17997987U JP H0186367 U JPH0186367 U JP H0186367U
- Authority
- JP
- Japan
- Prior art keywords
- line
- signal
- voltage
- circuit
- voltage comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000012935 Averaging Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Facsimile Image Signal Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Image Input (AREA)
Description
第１図は、本考案の２値化回路、第２図及び第
３図は従来例、第４図及び第６図は従来の２値化
回路の動作説明図、第７図は、本考案の２値化回
路の動作説明図である。
図中、３は電圧比較器、１１は１ライン遅延回
路、１２は１ライン平均化回路、１３は１画面平
均化回路、１４はパルス発生回路、１５は加算回
路、１６はサンプルホールド回路である。
Fig. 1 shows the binarization circuit of the present invention, Figs. 2 and 3 show conventional examples, Figs. 4 and 6 illustrate the operation of the conventional binarization circuit, and Fig. 7 shows the binarization circuit of the invention. FIG. 2 is an explanatory diagram of the operation of the binarization circuit of FIG. In the figure, 3 is a voltage comparator, 11 is a 1-line delay circuit, 12 is a 1-line averaging circuit, 13 is a 1-screen averaging circuit, 14 is a pulse generation circuit, 15 is an addition circuit, and 16 is a sample and hold circuit. .
補正 昭６３．２．１８
図面の簡単な説明を次のように補正する。
明細書第１１頁４行目に「第４図及び第６図は
」とあるを「第４図、第５図、及び第６図は」と
補正する。Amendment February 18, 1983 The brief description of the drawing is amended as follows. On page 11, line 4 of the specification, the phrase ``Figures 4 and 6'' has been amended to ``Figures 4, 5, and 6''.
Claims (1)
判別するための閾値電圧と比較することで実時間
に２値化する回路において、前記画像輝度信号を
１ライン分遅延させて、これを電圧比較器の被比
較電圧とし、１ライン単位で平均化した信号を１
ライン毎に取り込むとともに、これを１ライン期
間保持した信号を、前記１ライン分遅延させた信
号を積分した信号に重畳して、前記電圧比較器の
比較電圧としたことを特徴とする２値化回路。 In a circuit that binarizes an image luminance signal in real time by comparing it with a threshold voltage for discriminating white and black using a voltage comparator, the image luminance signal is delayed by one line and The voltage to be compared with the voltage comparator is the signal averaged for each line.
Binarization characterized in that a signal obtained line by line and held for one line period is superimposed on a signal obtained by integrating the signal delayed by one line and used as a comparison voltage of the voltage comparator. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17997987U JPH0186367U (en) | 1987-11-26 | 1987-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17997987U JPH0186367U (en) | 1987-11-26 | 1987-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0186367U true JPH0186367U (en) | 1989-06-07 |
Family
ID=31471519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17997987U Pending JPH0186367U (en) | 1987-11-26 | 1987-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0186367U (en) |
-
1987
- 1987-11-26 JP JP17997987U patent/JPH0186367U/ja active Pending
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