JPH0187242U - - Google Patents
Info
- Publication number
- JPH0187242U JPH0187242U JP18269487U JP18269487U JPH0187242U JP H0187242 U JPH0187242 U JP H0187242U JP 18269487 U JP18269487 U JP 18269487U JP 18269487 U JP18269487 U JP 18269487U JP H0187242 U JPH0187242 U JP H0187242U
- Authority
- JP
- Japan
- Prior art keywords
- alternating current
- current signal
- control
- circuit
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 3
- 230000002238 attenuated effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
Description
図１は本装置の一実施例である、静的コントロ
ール方式のブロツク図。図２は動作のタイムチヤ
ート図。図３は本装置の他の実施例の、動的コン
トロール方式のブロツク図。
図中、１は発振器、２は交流信号出力手段、２
１はゲート及び減衰回路、２２は定電流回路、３
は負荷、４は検知処理手段、４１は測定ゲート回
路、４１′は自主コントロール機能を内蔵した別
例の測定ゲート回路、４２は判定回路、４３は信
号処理回路、５はコントロール手段、５１は入力
信号処理回路、５２はタイミング信号発生回路、
６は不安定領域検知回路、Ｐ０〜Ｐ３１及びＩ０
〜Ｉ４１はブロツク間に伝送する各信号を示す。
FIG. 1 is a block diagram of a static control system, which is an embodiment of this device. FIG. 2 is a time chart of the operation. FIG. 3 is a block diagram of a dynamic control method of another embodiment of the present device. In the figure, 1 is an oscillator, 2 is an AC signal output means, 2
1 is a gate and attenuation circuit, 22 is a constant current circuit, 3
4 is a load, 4 is a detection processing means, 41 is a measurement gate circuit, 41' is another measurement gate circuit with a built-in self-control function, 42 is a judgment circuit, 43 is a signal processing circuit, 5 is a control means, 51 is an input a signal processing circuit; 52 is a timing signal generation circuit;
6 is an unstable region detection circuit, P0 to P31 and I0
~I41 indicates each signal transmitted between blocks.
Claims (1)
の出力の終末は暫次減衰する特性を構成する交流
信号出力手段と、概交流信号出力手段から出力さ
れる信号が、負荷に印加している時間内で検知、
測定、判定および処理を行う検知処理手段と、以
上の手段の作動のタイミングを行う自主コントロ
ールを含むコントロール手段で構成した負荷状態
検知装置。 An alternating current signal output means which outputs an alternating current signal for a predetermined period of time and has a characteristic that the end of the output is temporarily attenuated; Detected by
A load state detection device comprising a detection processing means that performs measurement, judgment, and processing, and a control means that includes self-control that controls the timing of the operation of the above means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18269487U JPH0187242U (en) | 1987-11-30 | 1987-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18269487U JPH0187242U (en) | 1987-11-30 | 1987-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0187242U true JPH0187242U (en) | 1989-06-08 |
Family
ID=31474138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18269487U Pending JPH0187242U (en) | 1987-11-30 | 1987-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0187242U (en) |
-
1987
- 1987-11-30 JP JP18269487U patent/JPH0187242U/ja active Pending
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