JPH01875A - Text blur prevention circuit in video circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a character blur prevention circuit in a video circuit such as a still image reproduction device.

BACKGROUND OF THE INVENTION In recent years, still image playback devices have been commercially available that magnetically record photographic images taken with a camera on a still image floppy disk and play the recorded images on a regular television. Here, the video signal is recorded on a plurality of tracks on the disk in a relationship of one track-one screen, that is, one rotation-one field. Then, such a video signal is read from the disk by a head, demodulated, and output.

By the way, a 1/2 interlaced scanning (so-called interlaced scanning) scheme is adopted in a normal television display system. For example, in the NTSC system like Japan, the number of horizontal scanning lines in one field is 262.5H, and the number of striped scanning lines for one screen in two fields, that is, one frame, is 52.
It is set to be 5H. When a still image disc or the like on which one field (ie, 262.degree. 5H horizontal scanning line) of video signals is recorded on one track is played back by such a television, the recording seam becomes a problem. In other words, the video signal on the same track (always the same video signal for each field) is read while the still image disc is continuously rotated, but at the recording joint (i.e., end point = start point) .5H1, that is, a shift of 1/2 of the horizontal synchronization period for each field. Therefore, if the image is reproduced as is on a normal television receiver, the screen will be distorted, making it impossible to display a normal still image.

Therefore, by alternately passing the 1-field repeated playback signal from the recording joint on the track through 0 and 5H delay circuits that correspond to 1/2 horizontal horizontal period for each field, and by synthesizing these signals, continuous horizontal synchronization can be achieved. It is necessary to create a playback signal.

For this reason, a block configuration as shown in FIG. 3 is generally adopted. First, after a video playback signal on a certain track read by the playback head 1 is amplified by the head amplifier 2, one side becomes a non-delayed through signal, and the other side becomes a through signal.
/2 horizontal period 0.58 through delay circuit 3,
The signal is input to the demodulation circuit (FM) 4 as a 5H delay signal. Here, in the demodulation circuit, these through signals and 0.5
H delay signal and switching pulse signal 5WP(Y
) (Y means a luminance signal) for each field. The demodulated signal is then separated by the synchronization signal separation circuit 5 as a composite synchronization signal (C-5ync), which is then passed through the synchronization signal generation circuit 6 to generate a synchronization signal, which is then combined with the signal demodulated by the demodulation circuit 4. The waveform synthesis circuit 7 synthesizes the signals and outputs them to the receiver as a frame signal (video signal).

Here, the switching pulse signal 5WP(Y) selects the through signal and the 0°5H delay signal by switching between the H level and the L level for each field as shown in FIG.゜5H delay period is generated, but the switching pulse signal s
Among these, wp(y) has a vertical through period (H level) during the 0°5H delay period, and is set in the through signal selection state only during the vertical synchronization period.

In the timing chart shown in FIG. 4, the video signal is placed between the horizontal synchronizing signals in the IH row. Also, near vertical synchronization, there are multiple equivalent pulses arranged in 0,5H,
Six of these equivalent pulses, ie, 3H, are used as the vertical synchronization signal (2). Before and after such a vertical synchronizing signal (2), there are also six equivalent pulses, that is, 3H's worth of 0.5H array (2) detection portions. Switching pulse signal 5WP
(Y) has a vertical through period of about 18 equivalent pulses within the 0.58 delay period,
Among them, the actual vertical synchronization signal (2) is detected and output as is as a through signal.

This is the basic method for preventing image blur for each field.

By the way, when playing such a still image, the characters of the track number in which the still image is recorded may be displayed on the screen together with the still image.

Such character information such as a track number is not written on the disc, but is processed by a circuit as shown in FIG. 5, for example. First, the microcomputer 8 writes data for determining the character display position to the character generation IC 9, and when the character generation IC 9 reaches the display position, the character data is outputted and displayed. At this time, the track number is displayed, for example, at the upper right position of the screen, but in any case, it is preferable to specify the position where the character is displayed and always display it at the same position. Therefore, the character generating IC 9 receives the vertical synchronizing signal SYnc through the integrating circuit 10 based on the composite synchronizing signal C-8ynC, and passes the horizontal synchronizing signal H-sync through a signal obtained by inverting the composite synchronizing signal C-3ync by the transistor 11. Receive 5 sync. Then, as shown in FIG. 6, the number of horizontal synchronization signals H-Sync is counted from the time (rising edge) when the vertical synchronization signal 5 sync is detected through the integrating circuit 10,
The track number characters are displayed at predetermined positions determined by the program, that is, at n H positions.

However, at the rising edge of the switching pulse signal 5WP(Y) at 3H from the falling edge of the pulse generator PG, which occurs once per rotation of the floppy disk, the broken line in FIG. Whisker-like switching noise as shown by pulse A may appear on the composite synchronization signal C-5sync.

Here, in order to determine the character display position of the track number, the horizontal synchronizing signal H-3 sync is counted sequentially from the rising edge of the vertical synchronizing signal SYNC, but this noise pulse A is also counted as 18 minutes. As a result, the nXH count value is about IH earlier than the through period, resulting in a display position of 18 minutes. Since such IH-shifted character display is repeated alternately, the l/rack number display becomes a blurred display state in which the characters flicker vertically.

A monostable circuit is provided that is set at the falling timing of a switching signal that switches between a 0.5H delay synchronized with a switching control signal and a through signal state, and the output of this monostable circuit and switching are An OR circuit is provided that generates a switching pulse by ORing with the control signal, and the switching pulse from this OR circuit is used to switch between vertical synchronization in a 0.58 delay period and vertical synchronization in a through signal state.

The action switching control signal has a low period of 4H and a high period of 9H from the fall of the pulse generator. 4 of the switching control signals to change the time until time-off of the monostable circuit, which is set at the timing of the falling edge of the switching signal.
If you make it H or higher and OR it with the switching control signal, the low period of 4H of the switching control signal becomes H.
goes high, and this output is used as a switching pulse between a signal delayed by 0.5H and a through signal. As a result, even if noise occurs during the low period of 4H of the switching control signal, there is virtually no effect, and even if the pulse generator fluctuates due to the jitter, the characters will not become blurred. It is.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 and 2. First, a monostable circuit 12 is provided which is set at the falling timing of a switching signal 5WP(C) that switches between a 0.5H delay synchronized with a switching pulse signal 5WP(Y) and a through signal state. 12
An OR gate 13 is connected to the Q output section of. A switching pulse signal swp(y) is input to the other input side of this OR gate 13. And the said OR
The gate 13 includes a switching circuit 14 that switches between a 0.5H delay vertical synchronization signal and a through signal state vertical synchronization signal.
is connected.

In such a configuration, the switching pulse signal 5W
P(Y) and the switching signal 5WP(C) are output synchronously, but the switching pulse signal swp(y) is 4H low from its falling edge (05, H delay).
9H is a High (through) period. Further, the switching signal 5WP(C) repeats a 0.58 delay and a through state at equal intervals.

Therefore, the monostable circuit 12 set by the switching pulse signal swp(y) is set longer than the 4H Low period of the switching pulse signal swp(y). Therefore, when the Q output of the monostable circuit 12 and the switching pulse signal 5WP(Y) are (7) ORed by the OR circuit 13, the switching pulse output from the (7) OR circuit 13 is the switching pulse signal 5WP. It becomes Locν at the timing 13H after (Y), and becomes Hi at the next rising edge of the switching pulse signal S W P (Y).
It becomes gh. Therefore, as shown in Figure 6 above, even if noise pulse A occurs, it is essentially the same as there is no noise pulse A, and the noise pulse does not enter the vertical synchronization signal. . Therefore, the switching pulse signal swp(y) basically does not appear, and even if it fluctuates due to the jitter component of the pulse generator, it does not cause blurring of characters.

Effects of the Invention As described above, the present invention provides a 0.
A monostable circuit is provided that is set at the falling timing of the switching signal that switches between the 5H delay and the through signal state, and an OR circuit that generates a switching pulse by ORing the output of this monostable circuit and the switching control signal. Set this OR
Since the switching pulse from the circuit switches between 0.58 delay period vertical synchronization and through signal state vertical synchronization, the time until the monostable circuit time-off, which is set at the falling edge of the switching signal, can be changed. If you make sure that the switching control signal is 4H or more, and take an OR with the switching control signal, the 4H of the switching control signal will be Low.
By using this output as a switching pulse between a signal delayed by 0.5H and a through signal when the period is High, even if noise occurs during the 4H Low period of the switching control signal, there is no substantial effect. Even if the pulse generator fluctuates due to the jitter, the characters will not be blurred.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing chart showing its operation, Fig. 3 is a circuit diagram showing general video signal processing, and Fig. 4 is a timing chart showing its operation. 5 is a circuit diagram showing a conventional example, and FIG. 6 is a timing chart showing its operation. 9... Character generation IC112... Monostable circuit, 13.
...OR circuit, swp(y)...switching pulse signal (switching control signal), 5WP(C)...switching signal ratio Requester Tokyo Electric Corporation

Claims (1)

[Claims] A composite synchronization signal in which a horizontal synchronization signal and a vertical synchronization signal are mixed is used, and a through period in which the video signal is output as a through signal, and the through signal is set to 0.5.
Output as a 0.5H delayed signal 0
．． Vertical synchronization is achieved by using a switching control signal that has a vertical through period that switches the 5H delay period for each field, and outputs the vertical synchronization signal in a through signal state without delay during vertical synchronization during the 0.5H delay period. In a character blur prevention circuit in a video circuit equipped with a character generation IC that counts the number of pulses of a horizontal synchronization signal in the composite synchronization signal based on signal detection and determines the output position of a displayed character, synchronization with a switching control signal is provided. 0.5
A monostable circuit is provided that is set at the falling timing of the switching signal that switches between the H delay and the through signal state, and an OR circuit that ORs the output of this monostable circuit and the switching control signal to generate a switching pulse. A circuit for preventing character blurring in a video circuit, characterized in that a switching pulse from the OR circuit switches between vertical synchronization of a 0.5H delay period and vertical synchronization of a through signal state.