JPH01893A - Digital speaker drive device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a digital speaker driving device.

(Prior Art) There have been various types of electrodynamic digital speakers in which sound is radiated by passing a driving current through a plurality of weighted voice coils according to signals of corresponding digits in a digital signal. A compositional format has been proposed.

(Problem to be solved by the invention) As is well known, in an electrodynamic speaker, the voice coil length is Q,
The magnetic flux density of the magnetic air gap where the voice coil is placed is B,
If the current flowing through the voice coil is defined as , then the driving force F generated in the voice coil, which is fixed to the bobbin of the voice coil integrated in the diaphragm, is expressed by F = B - Q / , so B When the magnitude of -Q is constant, the driving force F generated in the voice coil becomes proportional to the electric current flowing through the voice coil.

Therefore, if the mechanical impedance Zm of the vibration system excited by the driving force F generated by the voice coil is constant, the speed of the vibration system will always be proportional to the current flowing through the voice coil. (damper)
Since the mechanical impedance ′ changes non-linearly with the amount of displacement, non-linear distortion occurs in the acoustic output in the low frequency range where the amplitude of the diaphragm increases, so measures to improve this have been sought for a long time. .

Therefore, the present inventors first developed a method for detecting the voice coil position in an electrodynamic speaker equipped with a plurality of voice coils that are weighted in accordance with each digit of an input digital signal. a detection means, a difference detection means for detecting a difference signal between the force detected by the voice coil position detection means and the input digital signal; and a difference detection means for detecting a difference signal between the output of the difference detection means and the input digital signal. Driving a digital speaker consisting of an adding means for performing addition, and means for causing a drive current to flow through the voice coil of the corresponding digit according to the signal of each digit of the digital signal output from the adding means. We have proposed a device that successfully solves the above-mentioned problems.

A problem with the previously proposed digital speaker drive device described above is that it is difficult to remove aliasing noise that occurs during the digital-to-analog conversion operation of the digital speaker itself, which is equipped with a weighted voice coil. Ta.

(Means for Solving the Problems) The present invention provides an electrodynamic speaker equipped with a plurality of voice coils that are weighted in accordance with each digit of a digital signal, and an electrodynamic speaker that has an input digital signal over the input digital signal.

sampling means; voice coil position detection means for detecting the position of the voice coil of the electrodynamic speaker; and oversampling of the detection force by the voice coil position detection means and the input digital signal. difference detection means for detecting a difference signal between the signal obtained by oversampling the above-mentioned input digital signal; There is provided a digital speaker driving device comprising means for causing drive current to flow through the voice coils of the corresponding digits according to the signals of each digit of the digital signal outputted from the adding means, This solves the problems of the proposal.

(Example) Hereinafter, specific contents of the digital speaker driving device of the present invention will be explained in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of the digital speaker driving device of the present invention, and FIG.
FIG. 3 is a flowchart for explaining the operation, FIG. 4 is a timing chart for explaining the operation, FIG. 5 is a vertical side view of an example configuration of a digital speaker, and FIG. 6 is a block diagram showing an example configuration of a processor. A block diagram showing the functions of the digital signal processor, Fig. 7 is a block diagram of an example configuration of the drive section, and Fig. 8 is an oversampling block diagram.
FIG. 9 is a block diagram showing an exemplary configuration of the filter, FIG. 9 is a side view of the characteristic curve, and FIG. 10 is a block diagram showing the function of the oversampling filter shown in FIG. 8.

First, in the digital speaker SP shown in FIG. 5, 1 is a frame, and this frame 1 is fixed to a pole piece 2. As shown in FIG. 3 is a center pole, and this center pole 3 is arranged so that an annular magnetic gap 11 is formed between it and the center pole 2 when it is inserted into the circular hole bored in the above-mentioned pole piece 2. It is planted on the bottom plate 4.

Further, 5 is an annular permanent magnet, 6 is a coil bobbin fixed to the diaphragm 8, and this coil bobbin 6
has a plurality of voice coils 12 (shown as 12(2), 12(3) to 12(n) in FIG. ) is wound and fixed.

Reference numeral 7 denotes a center holder, and as is well known, the center holder 7 supports the coil bobbin 6 described above so that it can move in the magnetic gap 11 without contacting other parts. In the above-mentioned center holder 7, a so-called corrugation damper is used. Reference numeral 9 denotes a corrugated portion at the outer end of the diaphragm 8, the end of which is fixed to the frame 1, and the upper portion thereof is held down by a holding plate 10.

In FIG. 5, the components indicated by PG and PR are voice coil position detectors, and the voice coil position detector in the illustrated example uses one light emitting diode PG and one photodiode PR. Then, in Figure 4 (
At each time as illustrated in f), the light emitting diode P
The position of the voice coil can be detected by measuring each time value up to the time when the light emitted from G is received by the photodiode PR, as shown in (g) in Figure 4. It is said to be composed of In addition, in FIG. 5, for the sake of simplification of illustration, lead wires from a plurality of voice coils are not shown.

Now, a block diagram of an embodiment of a digital speaker driving device of the present invention (in the following explanation, the block diagram illustrated in FIG. 1 is assumed to be a digital speaker driving device for a left channel signal in a stereo signal). (It goes without saying that a digital speaker driving device for the right channel signal in a stereo signal is also shown by a block diagram similar to that in FIG. 1), 13 indicates a digital speaker. S
This is an input terminal for the digital signal that is being played back by P.

The input terminal 13 is supplied with an audio signal (hereinafter simply referred to as a digital signal) that is a digital signal of a predetermined signal format to be reproduced by a digital speaker. The digital signal supplied to the input terminal 13 described above is demodulated by the receiving section RD. PLL is a phase-locked loop, and this phase-locked loop PLL synchronizes the phase of the clock in the digital data obtained by demodulating in the receiver RD and the clock generated in the receiver RD. used for

It goes without saying that the input signal may be a serial signal or a parallel signal depending on the configuration of the device, but in the case of the configuration example shown in the first figure, the input terminal 13 It is said that the digital signal supplied to the terminal is a serial signal (see (a) in FIG. 4).

For example, the signal 1 demodulated by the receiving section RD described above.

The NRZ signal is given a pit clock signal from the receiving section RD and an address signal from the address decoder ADEC, and is supplied to a serial-to-parallel conversion circuit 5PCa that performs a required serial-to-parallel conversion operation.

The serial-to-parallel conversion circuit 5PCa converts the demodulated signal in the form of a serial signal in the receiving section RD supplied thereto into a parallel signal, and supplies it to the over-sampling filter O8D.

In the example shown in the first diagram, parallel 16-bit digital data X1 to X16 are supplied from the serial-to-parallel conversion circuit 5PCa to the input terminal of the oversampling filter O8D.

Also, when the signal DS goes high from the address decoder ADEC,
GH and LOW signals are supplied.

The above-mentioned oversampling filter O8D is 1
For example, a configuration as shown in FIG. 8 can be used. In the oversampling filter O3D shown in FIG. 8, CKSY, C shown in the timing control block
KO, DG, etc. are terminal names, and over/under in Figure 1.
The sampling filter O8D also has the above-mentioned terminal CKS.
Terminals corresponding to Y, CKO, etc. are shown.

The channel identification signal LRCK shown in FIG.
The terminal CK○ is supplied with an over voltage.
System clock signal XCLK (channel identification signal LR) that determines the calculation speed of sampling filter O5D
System clock XC when the repetition frequency of CK is fs and the digital filter shown in Figure 10 performs a digital filter operation such that p=59
The repetition frequency of LK is 980 fs. This system clock XCLK (generated in the above-mentioned receiving section RD) is supplied from the above-mentioned receiving section RD.

In FIG. 8, K-ROM is coefficient ROM, LAT C
H is a latch circuit, MPX is a multiplexer, P-P is a partial product generation circuit, SR is a shift register, W-TREE
is an adder block, ADD is a chiary look-ahead adder, and ACC is an accumulator. When 16-bit input (I NPUT) data X1 to X16 is given, it is output from the output terminal of the oversampling filter ○SD. The output data Y1 to Y18 ((e) in FIG. 4) are processed by the oversampling filter ○SD.
This is the 18-bit output data Y1-Y18 which has been bit-expanded by the operation of FIG.

The oversampling filter O3D shown in FIG. 8 has delay elements as shown by the signal flow graph shown in FIG. element)26.
27, and the multiplication of coefficients i (symbols representing coefficients aPwa p-2-・” b p-2t b p
By performing a predetermined filter calculation operation as a double oversampling filter using a multiplier linear phase FIR digital filter configuration consisting of a multiplier (marked with a multiplier) 28 and an adder 29, For example, a digital signal with frequency response characteristics as shown in Figure 9.
Since it operates as a filter, aliasing noise from digital speakers can be effectively removed.

That is, the delay time T in the delay element 27 shown in the signal flow graph shown in FIG.
1/88200) seconds, and the delay time 2T in the delay element 26 is (1/44100) seconds.
6-bit input data X1-X16 (1/44100
) seconds, the output terminal of the oversampling filter O8D outputs 18-bit output data Yl to Y18 every (1/88200) seconds ((e in Fig. 4).
)) is output, upsampled, and more.

Oversampling filter O5 for this example
The frequency response characteristic at D shows a characteristic that rapidly decreases from about 20 KHz to 24.1 KHz as shown in FIG. 9, and therefore a digital speaker without aliasing noise can be provided.

The other input terminal 15 in the digital signal processor DSP described above is supplied with a digital signal in the form of a parallel signal of the position data output from the serial/parallel conversion circuit 5pcb (see (i) in FIG. 4). , the digital signal in the form of a parallel signal (see (i) in FIG. 4) outputted from the above-mentioned serial-to-parallel conversion circuit 5pcb is the output signal (
(see (g) in Figure 4)) as an analog-digital converter AD.
A serial digital signal obtained by analog-to-digital conversion by C is converted into a parallel signal by serial-to-parallel conversion.

And the digital signal processor DS mentioned above
As P, for example, a configuration as illustrated in FIG. 2 can be used; however, in the digital signal processor shown in FIG.
U L a is a multiplier, MUX is a multiplexer, PC is a program counter, and DP is a data memory page.
pointer, ARP is an auxiliary register pointer, ALU is an arithmetic logic unit, ACC is an accumulator, and this digital signal processor DSP operates according to each step of the flowchart shown in FIG. It executes calculations corresponding to signal processing performed by the circuit configuration shown in the illustrated block diagram.

That is, in the digital signal processor DSP having the configuration shown in FIG. delay operator with 2T)
17, and the digital signal supplied to the input terminal 15 is also provided to the correction circuit 19.

The correction circuit 19 uses the position of the speaker voice coil in a state where the input signal to the speaker voice coil 12 is zero as a reference position, and also adjusts the difference between the input digital signal and the position data signal of the speaker voice coil. A negative feedback automatic control system using the signal as an error signal corrects the digital signal supplied to the input terminal 15 so that the position of the voice coil of the speaker can be made to correspond to the input digital signal. .

The output signal of the correction circuit 19 described above and the unit delay operator 18
The output signal from the adder 20 which outputs the difference with the output signal of is multiplied by a predetermined variable coefficient in the coefficient circuit 21 and supplied to the adder 22.

The digital signal a supplied to the input terminal 14 and the adder 22
Then, the output signal of the adder 22 described above is converted from two's complement notation to signed absolute value notation by a notation conversion circuit 23, and then sent to an output terminal 16.
is output to.

In the flowchart shown in the third figure for explaining the operation of the digital signal processor DSP described above,
When started, system initialization (step 1)
0o) is performed, and then in step 101 it is checked whether the BIO bar is zero or not, and if NO, the process returns to step 101 and YE
S, proceed to step 102, input digital signal a,
Next, the process advances to step 103 and a digital signal is input.

Then, the data enable signal DEN bar generated at that time causes the flip-flop FF to set the BIO bar to 1.
In step 104, the input digital signal is corrected, in step 105, the difference is detected, in step 106, it is multiplied by , in step 107- it is added to the input digital signal a, and in step 108, the upper 16 The bit and the lower two bits are output and the process returns to step 101.

The signals of each digit in the digital signal in the form of a parallel signal (parallel 18-bit data in some examples) output from the output terminal 16 of the digital signal processor DSP described above are input to the input side of the drive unit DRV of the digital speaker. Input terminal 24 for each digit (input terminal 24 corresponds to each digit of the digital signal individually, 24 (1) to 24 in Fig. 7)
24 (n)).

An example configuration of the digital speaker drive unit DRV is shown in FIG.

In FIG. 7, DRVa is an on/off control unit for each digit of the digital signal, DRVb is a power supply voltage polarity setting unit, and LTVE(1) to LTVE(n) are write enable signals WE. bar and address decoder A
This is a latch circuit that latches an input signal by AND outputting with HIGH2 of signal DS from DEC and AND outputting with LOW2 of signal DS from write enable signal WE bar and address decoder ADEC. (1) to LTOE(n) are shown in (d) in Figure 4.
It is a latch circuit that latches an input signal using a clock signal WCLK shown in
5W(n) is an analog switch, R1-R6 are resistors,
GOMP is a comparator, Ql, Q2 are transistors, 24(
1) to 24(n) are input terminals, 25 (1) to 25 (
n) is an output terminal.

Output terminal 16 of digital signal processor DSP
to the input terminal 24 of the digital speaker drive unit DRV.
Input terminal 24 to which the most significant digit signal of the digital signals supplied to (1) to 24 (n) is supplied.
(1) and output terminal 25 (1), latch circuits LTwE (1), LTOE (1), resistors R1 to R6,
In the flt source voltage setting unit DRVb, which is composed of a comparator COMP, transistors Ql, 02, etc.,
When the most significant digit signal of the input digital signal supplied to its input terminal 24 (1) is 0, the output terminal 25 (
If the positive DC power supply voltage +V c c is sent from 1), and the most significant digit of the input digital signal is 1,
Negative DC power supply voltage -V c from output terminal 25 (1)
Each voice coil 12 (2) to which a predetermined weighting is applied in the digital speaker SP by sending out the
12(n) in common at one end.

In addition, each digit of the input digital signal supplied from the output terminal 16 of the digital signal processor DSP to the drive unit DRV of the digital speaker from the input signal of the least significant digit to the signal of the digit next to the most significant digit The input terminals 24 (n) of each digit are individually supplied with the input signals of (n), .
・Between 24 (3), 24 (2) and terminals 25 (n), ... 25 (3), 25 (2) connected to analog switches corresponding to the signals of each digit mentioned above, respectively. , latch circuits LTWE(n) to L TW[E
(2), LTOE(n) to predetermined ones of LTOE(2), and analog switches 5W(n) to 5W(
In the on/off control unit DRVa that performs on/off control of each digit signal in the digital signal configured by 2), each voice coil 12(n) to 12(2) to which a predetermined weighting is applied in the digital speaker SP. Analog switch 5W(n) to 5W(2) connected to
is selectively controlled on and off to cause a current to flow through a selected predetermined voice coil according to the voltage appearing at the output terminal 25 (1) of the voltage polarity setting section DRVb.

That is, the latch circuits L TWE (1) to L TυE (n) shown in FIG.
At the timing of the write enable WE bar shown in Q), the corresponding input terminals 24 (
1) to 24 (n), and latch circuits LTOE(1) to LTOE(
n) is the clock signal W shown in FIG.
At the timing of CLK, the digital signals latched in the corresponding tailing latch circuits L TWE(1) to L TIE(n) are latched.

Therefore, the latch circuits LTOE(1) to LTO
Predetermined weighting is applied to the digital speaker SP connected to the analog switches 5W(n) to 5W(2) which are turned on and off by the output signal of E(n). Power supply voltage polarity setting unit DRV for each voice coil
A current is caused to flow by the voltage appearing at the output terminal 25 (1) of the digital speaker SP, and the voice coil 1 of the digital speaker SP
2 is displaced.

Then, the digital speaker SP is displaced as described above.
The detection force from the voice coil position detection means for detecting the position of the voice coil 12 is used in the difference detection means to detect a difference signal between the input digital signal and the input digital signal.
Next, the output of the difference detection means described above is added to the input digital signal described above, and then a drive current is caused to flow through the voice coil of the corresponding digit according to the signal of each digit of the digital signal. Even during large amplitude driving that causes non-linear distortion in the center retainer 7,
Alternatively, even when driven with a small amplitude, the digital speaker is driven so that the position of its voice coil correctly corresponds to the input digital signal.

(Effects of the Invention) As is clear from the detailed explanation above, the digital speaker driving device of the present invention is as follows.

an electrodynamic speaker having a plurality of voice coils weighted to correspond to each digit of a digital signal; means for oversampling an input digital signal; a voice coil position detection means to be detected; a difference detection means for detecting a difference signal between the detection force of the voice coil position detection means and a signal obtained by oversampling the input digital signal; An addition means that adds the output of the difference detection means described above and a signal obtained by oversampling the input digital signal described above, and a signal of each digit of the digital signal outputted from the addition means described above correspond to each other. and a means for causing a drive current to flow through the voice coils of the above-mentioned digits.
The digital speaker driving device of the present invention uses a negative feedback automatic control system that uses the difference signal between the input digital signal and the position data signal of the voice coil of the speaker as an error signal.
Since the voice coil is driven so that the position of the speaker's voice coil corresponds to the input digital signal, the digital・Not only can the speaker be driven so that the position of its voice coil corresponds correctly to the input digital signal, but also aliasing noise is generated because the input digital signal is oversampled by the oversampling means. The occurrence of can be effectively prevented and also.

Since bit expansion is performed by the oversampling means, a speaker with a wider dynamic range can be provided by using an electrodynamic speaker with an increased number of voice coils corresponding to the bit expansion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a digital speaker driving device according to the present invention, FIG. 2 is a block diagram showing an example configuration of a digital signal processor, FIG. 3 is a flowchart for explaining the operation, and FIG. The figure is a timing chart for explaining operation, Figure 5 is a vertical side view of an example configuration of a digital speaker, Figure 6 is a block diagram showing the functions of a digital signal processor, and Figure 7 is an example configuration of a drive section. Fig. 8 is a block diagram showing an example configuration of the over-sampling filter, Fig. 9 is a side view of the characteristic curve, and Fig. 10 is a block diagram showing the functions of the over-sampling filter shown in Fig. 8. be. DESCRIPTION OF SYMBOLS 1... Frame, 2... Pole piece, 3... Center pole, 4... Bottom plate, 5... Annular permanent magnet, 6... Coil bobbin fixed to the diaphragm 8,
7... Center holder, 9... Corrugated portion at the outer end of the diaphragm 8, 11... Annular magnetic gap, 12...
・Multiple voice coils 12 (12 (2), 12 (3) ~
12(n)), 13... An input terminal for a digital signal to be reproduced by the digital speaker SP, 14.
15... Input terminal in digital signal processor DSP, 16... Output terminal of digital signal processor DSP, 17... Delay operator, 19.
...Correction circuit, 20.22...Adder, 21...Coefficient circuit, 23...Notation conversion circuit for converting from two's complement notation to signed absolute value notation, 24...Digital speaker drive Input terminal 24 (of each digit on the input side in section DRV)
24(1)-24(n)), 25(1)-25(n)・
...Output terminal, SP...Digital speaker, PG...
...Light emitting diode, PR...Photodiode, R
D...Reception section, PLL...Phase locked loop, ADEC...Address decoder, 5PCa, 5
PCb...Serial-to-parallel conversion circuit, MULa...Multiplier,
MUX...multiplexer, PC...program counter, DP...data memory page pointer, ARP...auxiliary register pointer, ALU...
Arithmetic logic unit, ACC...accumulator. DRV...Digital speaker drive unit, DRV
a...On/off control unit for each digit signal in the digital signal, ADC...analog-to-digital conversion circuit. FF...Flip prop, DRVb...Power supply voltage polarity setting unit, LTljE(1) to LTWf! (n
)... Latch circuit that latches the input signal by the write enable signal WE bar, L TOE (1) ~L
TOE(n) - A latch circuit that latches an input signal using a clock signal WCLK, 5W(2) to 5W(n).
...Analog switch, R1-R6...Resistance, GO
MP... Hi Soki, Ql. Ql...Transistor, O8D...Over sampling filter. NPLIT

Claims (1)

[Claims] 1. An electrodynamic speaker equipped with a plurality of voice coils weighted in accordance with each digit of a digital signal, and means for oversampling an input digital signal;
A voice coil position detection means for detecting the position of the voice coil of the electrodynamic speaker described above, a detection force by the voice coil position detection means described above, and a signal obtained by oversampling the input digital signal described above; difference detecting means for detecting a difference signal of the above, addition means for adding the output of the above-mentioned difference detecting means and a signal obtained by oversampling the above-mentioned input digital signal; A digital speaker driving device 2 includes means for causing drive current to flow through the voice coils of the corresponding digits according to signals of each digit of the digital signal; A digital speaker driving device according to claim 1, which uses an electrodynamic speaker in which the number of voice coils is increased in response to expansion.