JPH0191352U - - Google Patents
Info
- Publication number
- JPH0191352U JPH0191352U JP18740587U JP18740587U JPH0191352U JP H0191352 U JPH0191352 U JP H0191352U JP 18740587 U JP18740587 U JP 18740587U JP 18740587 U JP18740587 U JP 18740587U JP H0191352 U JPH0191352 U JP H0191352U
- Authority
- JP
- Japan
- Prior art keywords
- unit
- resonant circuit
- data
- signal
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Near-Field Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第1図は本考案のデータ通信装置の一実施例に
よる物品識別システムの書込/読出制御ユニツト
の構成を示すブロツク図、第2図はその全体構成
を示すブロツク図、第3図はIDユニツトの構成
を示すブロツク図、第4図は書込/読出制御ユニ
ツトよりIDユニツトにデータを伝送する際の各
部の波形を示すタイムチヤート、第5図はIDユ
ニツトより書込/読出制御ユニツトに信号を伝送
する際の各部の波形を示すタイムチヤートである
。
1……書込/読出制御ユニツト、3……IDユ
ニツト、4……制御機器、L1,L2,L3……
コイル、11……クロツク発生器、12……タイ
ムコントローラ、13……送信パルス発生回路、
14……受信ゲート信号発生回路、15……発振
器、17,30……共振回路、18,21……ア
ナログスイツチ、22,31……検波回路、25
……サンプルホールド回路、26,32……比較
器、27……共振制御手段、33……カウンタ、
34……デジタルコンパレータ、36……メモリ
制御部、37……メモリ、38……残留制御パル
ス発生器、41……電池、42……データ復調手
段、43……残響制御手段。
FIG. 1 is a block diagram showing the configuration of a write/read control unit of an article identification system according to an embodiment of the data communication device of the present invention, FIG. 2 is a block diagram showing its overall configuration, and FIG. 3 is an ID unit. FIG. 4 is a time chart showing the waveforms of each part when data is transmitted from the write/read control unit to the ID unit, and FIG. This is a time chart showing the waveforms of each part when transmitting. 1...Write/read control unit, 3...ID unit, 4...Control equipment, L1, L2, L3...
Coil, 11...Clock generator, 12...Time controller, 13...Transmission pulse generation circuit,
14... Reception gate signal generation circuit, 15... Oscillator, 17, 30... Resonance circuit, 18, 21... Analog switch, 22, 31... Detection circuit, 25
... Sample and hold circuit, 26, 32 ... Comparator, 27 ... Resonance control means, 33 ... Counter,
34...Digital comparator, 36...Memory control unit, 37...Memory, 38...Residual control pulse generator, 41...Battery, 42...Data demodulation means, 43...Reverberation control means.
Claims (1)
データの半二重データ伝送を行うデータ通信装置
であつて、 前記第1のユニツトは、 前記第2のユニツトに対向する面に設けられた
第1のコイルを有する発振器と、 データ送信時には送信データ信号に対応させて
第1、第2のデユーテイ比を有し、データ受信時
には一定の第3のデユーテイ比を有する一定周期
の送信パルス信号を発生し、前記発振器に該一定
周期の送信パルス信号を与えることによつてその
発振を断続する送信パルス発生手段と、 前記発振器の発振周波数に実質的に等しい共振
周波数を有し、前記第2のユニツトに対向する面
に設けられた第2のコイルを含む第1の共振回路
と、 前記送信パルス発生手段の送信パルスに対応し
た信号が与えられ前記発振器の発振停止時のタイ
ミングを有する受信ゲート信号を発生する受信ゲ
ート信号発生手段と、 前記第1の共振回路に並列に設けられ、前記受
信ゲート信号によつて断続されるアナログスイツ
チと抵抗の直列接続体を有し、前記第1の共振回
路のQを制御する共振制御手段と、 前記受信ゲート信号発生手段の受信ゲート信号
が与えられる間に前記第1の共振回路に得られる
電磁誘導信号を検波する検波回路と、 前記受信ゲート信号の所定タイミングで前記検
波回路の出力をサンプリングするサンプルホール
ド回路と、 前記サンプルホールド回路のホールド信号を所
定レベルで弁別する第1の比較器と、を有するも
のであり、 前記第2のユニツトは、 前記第1のユニツトの発振器の発振周波数に実
質的に等しい共振周波数を有し前記第1のユニツ
トに対向する面に設けられた第3のコイルを含む
第2の共振回路と、 前記第2の共振回路に得られる信号を検波する
検波回路と、 前記検波出力を所定の閾値レベルで弁別するこ
とによつて送信パルス信号を得る第2の比較器と
、 前記第1のユニツトからのデータ受信時に前記
第2の比較器の出力に基づいて第1、第2のデユ
ーテイ比の送信パルス信号より送信データ信号を
復調するデータ復調手段と、 前記第2の共振回路とアース間に接続されたス
イツチング素子を有し、前記第1のユニツトへの
データ伝送時に前記第2の比較器より得られる第
3のデユーテイ比の送信パルス信号に基づいて前
記発振器の発振停止のタイミングで該スイツチン
グ素子を送信データに対応させて断続することに
より第2の共振回路に生じる残響を制御する残響
制御手段と、を有することを特徴とするデータ通
信装置。[Claims for Utility Model Registration] A data communication device that performs half-duplex data transmission of serial data between a first unit and a second unit, wherein the first unit is opposite to the second unit. an oscillator having a first coil provided on a surface that transmits data; a transmission pulse generating means that generates a transmission pulse signal with a certain period and intermittents the oscillation by providing the transmission pulse signal with a certain period to the oscillator; a first resonant circuit including a second coil provided on a surface facing the second unit; and a first resonant circuit including a second coil provided on a surface facing the second unit; a receiving gate signal generating means for generating a receiving gate signal having timing, and a series connection body of an analog switch and a resistor that are provided in parallel with the first resonant circuit and are switched on and off by the receiving gate signal, resonance control means for controlling the Q of the first resonant circuit; a detection circuit for detecting an electromagnetic induction signal obtained in the first resonant circuit while a reception gate signal of the reception gate signal generation means is applied; a sample hold circuit that samples the output of the detection circuit at a predetermined timing of the reception gate signal; and a first comparator that discriminates the hold signal of the sample hold circuit at a predetermined level; a second resonant circuit including a third coil having a resonant frequency substantially equal to the oscillation frequency of an oscillator of the first unit and provided on a surface facing the first unit; a detection circuit that detects a signal obtained in the second resonant circuit; a second comparator that obtains a transmission pulse signal by discriminating the detection output at a predetermined threshold level; data demodulation means for demodulating the transmitted data signal from the transmitted pulse signals of the first and second duty ratios based on the output of the second comparator when receiving the data; and connected between the second resonant circuit and ground. The switching element is configured to switch the oscillator at the timing of stopping oscillation of the oscillator based on a transmission pulse signal of a third duty ratio obtained from the second comparator during data transmission to the first unit. 1. A data communication device comprising: reverberation control means for controlling reverberation occurring in the second resonant circuit by intermittent transmission in accordance with transmitted data.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18740587U JPH0543550Y2 (en) | 1987-12-09 | 1987-12-09 | |
| EP88120656A EP0320015B1 (en) | 1987-12-09 | 1988-12-09 | Inductive data communicating apparatus |
| AT88120656T ATE108965T1 (en) | 1987-12-09 | 1988-12-09 | INDUCTIVE DATA TRANSMISSION SYSTEM. |
| DE3850753T DE3850753T2 (en) | 1987-12-09 | 1988-12-09 | Inductive data transmission system. |
| US08/068,263 US5313198A (en) | 1987-12-09 | 1993-05-28 | Data communication apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18740587U JPH0543550Y2 (en) | 1987-12-09 | 1987-12-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0191352U true JPH0191352U (en) | 1989-06-15 |
| JPH0543550Y2 JPH0543550Y2 (en) | 1993-11-02 |
Family
ID=31478562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18740587U Expired - Lifetime JPH0543550Y2 (en) | 1987-12-09 | 1987-12-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0543550Y2 (en) |
-
1987
- 1987-12-09 JP JP18740587U patent/JPH0543550Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543550Y2 (en) | 1993-11-02 |
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