JPH0193196A - Printed circuit substrate - Google Patents
Printed circuit substrateInfo
- Publication number
- JPH0193196A JPH0193196A JP62250523A JP25052387A JPH0193196A JP H0193196 A JPH0193196 A JP H0193196A JP 62250523 A JP62250523 A JP 62250523A JP 25052387 A JP25052387 A JP 25052387A JP H0193196 A JPH0193196 A JP H0193196A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- tab semiconductor
- tab
- circuit board
- circuit substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K1/183—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components mounted in and supported by recessed areas of the PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント回路基板に関し、特にＴＡＢ半導体装
置を表面実装するプリント回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed circuit board, and particularly to a printed circuit board on which a TAB semiconductor device is surface mounted.
第３図は従来のプリント回路基板にＴＡＢ半導体装置を
実装した場合の断面構造図で、ＴＡＢ半導体装置２は一
主面上に回路パターンを形成する回路基板１の平坦な主
面上にチップ表面を下に向けて実装され、リード３と基
板配線（図示しない）とが接続される。FIG. 3 is a cross-sectional structural diagram of a TAB semiconductor device mounted on a conventional printed circuit board. The lead 3 and the board wiring (not shown) are connected to each other.
このように、従来のプリント回路基板では、基板上に’
ｒ’ Ａ Ｂ半導体装置をチップ表面を下に向けて載直
し基板配線との間をリード接続しているので、リード・
フレームまたはケースにマウントされた通常の半導体装
置のように、チップの裏面を通して半導体基板に電位を
与えることができない。従って実装されたＴＡＢ半導体
装置の動作特性が安定しないという不都合が生じる。In this way, in conventional printed circuit boards, '
r' A B Since the semiconductor device is remounted with the chip surface facing down and the leads are connected to the board wiring, the leads and
Unlike a normal semiconductor device mounted on a frame or case, it is not possible to apply a potential to the semiconductor substrate through the backside of the chip. Therefore, there arises a problem that the operating characteristics of the mounted TAB semiconductor device are not stable.
本発明の目的は、上記の情況に鑑み、チップの半導体基
板に所要の電位を与え得る状態でＴＡＢ半導体装置装実
装することのできるプリント回路基板を提供することで
ある。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a printed circuit board on which a TAB semiconductor device can be mounted in a state where a required potential can be applied to a semiconductor substrate of a chip.
本発明によれば、プリント回路基板は、一方の主面上に
所要の回路パターンと実装すべきＴＡＢ半導体装置に見
合う大きさの貫通孔を備える回路基板と、前記回路基板
の他方の主面に固着される金属薄板とを含む。According to the present invention, a printed circuit board includes a circuit board having a through hole of a size commensurate with a required circuit pattern and a TAB semiconductor device to be mounted on one main surface, and a circuit board having a through hole of a size commensurate with a required circuit pattern and a TAB semiconductor device to be mounted on one main surface, and and a thin metal plate to which it is fixed.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示すＴＡＢ半導体装置の実
装断面構造図である。本実施例によれば、本発明のプリ
ント回路基板は、一方の主面上に所要の回路パターン（
図示しない）およびＴＡＢ半導体装置１２に見合う大き
さの貫通孔１４とをそれぞれ備える回路基板１１と、こ
の回路基板の他方の主面に固着される金属薄板１５とを
含む。本実施例によれば、ＴＡＢ半導体装置１２は底部
を金属薄板１５で塞がれた回路基板１１上の貫通孔１４
内にチップ表面を上に向け、また、裏面が金属薄板１５
の電気的に接続された状態で載置され実装される。ここ
で１３はＴＡＢ半導体装置１２のリードである。従って
、本実施例に従えば、金属薄板１５に電源電位（ＴＡＢ
半導体装置１２がＮ型基板の場合）または接地電位（Ｔ
ＡＢ半導体装置１２がＰ型基板の場合）を与えることに
よ って、回路基板１１上に実装されたＴＡＢ半導体装
置１２の動作特性を安定化することができる。FIG. 1 is a sectional view of the mounting structure of a TAB semiconductor device showing one embodiment of the present invention. According to this embodiment, the printed circuit board of the present invention has a required circuit pattern (
(not shown) and a through hole 14 having a size corresponding to the TAB semiconductor device 12, respectively, and a thin metal plate 15 fixed to the other main surface of the circuit board. According to this embodiment, the TAB semiconductor device 12 has a through hole 14 on the circuit board 11 whose bottom portion is closed with a thin metal plate 15.
Inside, the chip surface is facing up, and the back side is the thin metal plate 15.
The device is placed and mounted in an electrically connected state. Here, 13 is a lead of the TAB semiconductor device 12. Therefore, according to this embodiment, the thin metal plate 15 has a power supply potential (TAB
when the semiconductor device 12 is an N-type substrate) or the ground potential (T
When the AB semiconductor device 12 is a P-type substrate), the operating characteristics of the TAB semiconductor device 12 mounted on the circuit board 11 can be stabilized.
第２図は本発明の他の実施例を示すＴＡＢ半導体装置の
実装断面構造図である０本実施例によれば、本発明のプ
リント回路基板は、一方の主面−Ｅに所要の回路パター
ンとＴＡＢ半導体装置１２ａまたは１２ｂに見合う大き
さの貫通孔１４ａまたは１２ｂをそれぞれ備えた回路基
板１１ａおよび１１ｂと、この回路基板１１ａ、ｌｌｂ
の他方の主面に挟まれて固着される一つの金属薄板１５
とを含む。ここでＴＡＢ半導体装１１２ａ、１２ｂは底
部をそれぞれ金属薄板１５で塞がれた回路基板１１ａ、
ｌｌｂの貫通孔１４ａ、１４ｂ内にそれぞれチップ表面
を外に向け、また、裏面が金属薄板１５と電気的に接続
された状態で載置され実装される。従って、本実施例に
従えば、金属薄板１５を介し上下２組のＴＡＢ半導体装
置１２ａ。FIG. 2 is a cross-sectional view of the mounting structure of a TAB semiconductor device showing another embodiment of the present invention.According to this embodiment, the printed circuit board of the present invention has a required circuit pattern on one main surface -E. and TAB circuit boards 11a and 11b each having a through hole 14a or 12b of a size suitable for the semiconductor device 12a or 12b;
One thin metal plate 15 sandwiched between and fixed to the other main surface of
including. Here, the TAB semiconductor devices 112a and 12b each have a circuit board 11a whose bottom is covered with a thin metal plate 15,
The chip is placed and mounted in the through holes 14a and 14b of the ILB with the front surface facing outward and the back surface being electrically connected to the thin metal plate 15. Therefore, according to this embodiment, two sets of upper and lower TAB semiconductor devices 12a are connected with the thin metal plate 15 interposed therebetween.
１２ｂの基板電位が安定化されるので高密度実装を行う
ことができる。Since the substrate potential of 12b is stabilized, high-density mounting can be performed.
以上詳細に説明したように、本発明によれば、回路基板
の他方の主面に固着した金属薄板を介し一方の主面上に
載置されたＴＡＢ半導体装置の基板にそれぞれ所要の電
位を与えることができるので、実装したＴＡＢ半導体装
置の動作特性を安定化させることができる。As explained in detail above, according to the present invention, a required potential is applied to each substrate of a TAB semiconductor device placed on one main surface of the circuit board via a thin metal plate fixed to the other main surface of the circuit board. Therefore, the operating characteristics of the mounted TAB semiconductor device can be stabilized.
第１図は本発明の一実施例を示すＴＡＢ半導体装置の実
装断面構造図、第２図は本発明の他の実施例を示すＴＡ
Ｂ半導体装置の実装断面構造図、第３図は従来のプリン
ト回路基板にＴＡＢ半導体装置を実装した場合の断面構
造図である。
１．１１．１１ａ、１ ｌｂ・−・回路基板、２゜１２
．１２ａ、１２ｂ−−・ＴＡＢ半導体装置、３゜１３
・・・リード、１４．１４ａ、 １４ｂ−貫通孔、１５
・・・金属薄板。FIG. 1 is a cross-sectional diagram of the mounting structure of a TAB semiconductor device showing one embodiment of the present invention, and FIG. 2 is a TAB semiconductor device mounting structure diagram showing another embodiment of the present invention.
FIG. 3 is a cross-sectional structural diagram of a TAB semiconductor device mounted on a conventional printed circuit board. 1.11.11a, 1 lb.--Circuit board, 2゜12
．． 12a, 12b--TAB semiconductor device, 3°13
...Lead, 14.14a, 14b-through hole, 15
...Thin metal plate.
Claims (1)
Ｂ半導体装置に見合う大きさの貫通孔を備える回路基板
と、前記回路基板の他方の主面に固着される金属薄板と
を含むことを特徴とするプリント回路基板。Required circuit pattern and TA to be mounted on one main surface
B. A printed circuit board comprising: a circuit board having a through hole of a size suitable for a semiconductor device; and a thin metal plate fixed to the other main surface of the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62250523A JPH0193196A (en) | 1987-10-02 | 1987-10-02 | Printed circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62250523A JPH0193196A (en) | 1987-10-02 | 1987-10-02 | Printed circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0193196A true JPH0193196A (en) | 1989-04-12 |
Family
ID=17209157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62250523A Pending JPH0193196A (en) | 1987-10-02 | 1987-10-02 | Printed circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193196A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0320051A (en) * | 1989-03-20 | 1991-01-29 | Seiko Epson Corp | Semiconductor device mounting structure and mounting method and mounting device |
| JPH0537121A (en) * | 1991-01-30 | 1993-02-12 | Mitsui High Tec Inc | Semiconductor device packaging substrate and package method of semiconductor device using it |
| CN105917749A (en) * | 2014-01-13 | 2016-08-31 | 自动电缆管理有限公司 | Circuit board, circuit and method for manufacturing circuit |
-
1987
- 1987-10-02 JP JP62250523A patent/JPH0193196A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0320051A (en) * | 1989-03-20 | 1991-01-29 | Seiko Epson Corp | Semiconductor device mounting structure and mounting method and mounting device |
| JPH0537121A (en) * | 1991-01-30 | 1993-02-12 | Mitsui High Tec Inc | Semiconductor device packaging substrate and package method of semiconductor device using it |
| CN105917749A (en) * | 2014-01-13 | 2016-08-31 | 自动电缆管理有限公司 | Circuit board, circuit and method for manufacturing circuit |
| CN105917749B (en) * | 2014-01-13 | 2019-05-07 | 自动电缆管理有限公司 | Circuit board, circuit and method for making circuit |
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