JPH0193280A - Synchronizing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization circuit for stably receiving data multiplexed in a data channel area of a PCM audio data signal of satellite broadcasting.

Conventional satellite broadcasting includes data broadcasting in which information data is multiplexed and transmitted in a data channel area of a PCM audio data signal. In order to receive the data broadcasting, the BS
A synchronization circuit is required to create a superframe synchronization signal and a mode switching synchronization signal from the audio bitstream signal output from the tuner.

FIG. 3 is an example of a conventional synchronous circuit. 21 is a bit stream signal input terminal output from the BS tuner, and 22 is a clock input terminal output from the BS tuner. The bit stream signal inputted from the input terminal 21 and the clock inputted from the clock input terminal 22 are inputted to the shift register circuit 23, and the shift register circuit 23 takes in the bit stream signal for each clock and inputs the data. It is output to the latch circuit 24.

On the other hand, 26 is an input terminal for inputting a frame synchronization signal outputted from the BS tuner, and the frame synchronization signal inputted from the input terminal 25 is inputted to the frame synchronization signal output terminal 26 and the timing generation circuit 27. In the timing generation circuit 27, the input frame synchronization signal and
Based on the input clock, a timing signal for latching the frame control code part of the bit stream signal is output to the latch circuit 24. In the launch circuit 24,
The timing signal launches the data output from the shift register circuit 23, and outputs the mode switching synchronization signal to the output terminal 28 for outputting the mode switching synchronization signal, and outputs the superframe synchronization signal to the output terminal 29 for the superframe synchronization signal. Output a signal.

Problems to be Solved by the Invention In satellite broadcasting, when it rains heavily, radio waves from the satellite are attenuated and errors occur in the frame control code portion of the bit stream signal output from the BS tuner. If the above-mentioned error occurs, if the conventional synchronization circuit is used, the error will occur in the superframe synchronization signal and the mode switching synchronization signal, which will have a great negative impact on the reception of data multiplexed in the data channel area. It was affecting me.

The present invention stabilizes the super frame synchronization signal and the mode switching signal even when the radio waves are attenuated and the error occurs, compared to the conventional example, and the present invention stabilizes the super frame synchronization signal and the mode switching signal even when the radio waves are attenuated and the error occurs. The object is to provide a synchronous circuit that can prevent adverse effects as much as possible.

Means for Solving the Problems The present invention adds to the conventional circuit a divide-by-9 circuit that divides the frame synchronization signal by nine, and a phase difference between the super frame synchronization signal and the output of the divide-by-9 circuit. , a super frame phase synchronization circuit that outputs a super frame synchronization pulse signal to the divide-by-9 circuit to match the phase of the super frame synchronization signal only when a phase mismatch occurs a certain number of times in succession, and a divide-by-9 frequency circuit. The phase of the mode switching synchronization signal and the output of the 10 frequency divider circuit is compared with the output of the 10 frequency divider circuit that divides the output of the circuit by 10, and only when a phase mismatch occurs a certain number of times in a row, The configuration includes a mode switching phase synchronization circuit that outputs a mode switching synchronization pulse signal to the frequency dividing circuit to match the phase of the mode switching synchronization signal.

According to the present invention, with the above-described configuration, even if an error occurs in each of the super frame synchronization signal and the mode switching synchronization signal, it can be compensated for up to a consecutive part υ that is less than or equal to an arbitrarily set number of times, and the data channel This is very effective for stably receiving data multiplexed in an area.

Embodiment FIG. 1 shows a block configuration of a synchronous circuit which is an embodiment of the present invention. In FIG. 1, 1 is a terminal for inputting a bit stream signal output from a BS tuner (not shown), and 2 is a terminal for inputting a clock output from the BS tuner. The bitstream signal input from terminal 1 and the clock input from terminal 2 are
The data is input to a shift register circuit 3, which takes in the bit stream signal every clock and outputs the data to a latch circuit 4.

Further, 6 is a terminal for inputting a frame synchronization signal outputted from the BS tuner, and the frame synchronization signal inputted from the terminal 6 is inputted to the terminal 6 for outputting a frame synchronization signal, the timing generation circuit 7, etc. In the timing generation circuit 7, the frame synchronization signal inputted from the terminal 6, the clock inputted from the terminal 2, and the timing signal for latching the frame control code part of the bit stream signal are sent to the latch circuit 4. Output. In the latch circuit 4, the shift register circuit 3
The output data is latched and the phase synchronization circuit 8
A super frame synchronization signal is output to the phase synchronization circuit 9.
Outputs a mode switching synchronization signal to.

On the other hand, the frame synchronization signal inputted from the terminal 5 is frequency-divided by nine in a frequency-dividing circuit 11 and outputted to the phase synchronization circuit 8 and a terminal 11 for outputting a superframe synchronization signal. The phase synchronization circuit 8 compares the phases of the output of the launch circuit 4 and the output of the divide-by-9 circuit 1o, and only when a phase mismatch occurs a certain number of times in succession, the divide-by-9 circuit 10 sends a super frame. Outputs a synchronous pulse signal. 9 frequency divider circuit 10
Now, only when the superframe synchronization pulse signal is output from the phase synchronization circuit 8, the phase of the signal output to the terminal 11 and the phase synchronization circuit 8 is changed to the timing at which the superframe synchronization pulse signal is output.

Furthermore, the signal output from the 9 frequency divider circuit 10 is inputted to the 1o frequency divider circuit 12, where the signal is divided by 1o, and the signal is input to the phase synchronized circuit 9.
and is output to the mode switching synchronization signal output terminal 13.

The phase synchronization circuit 9 compares the phases of the output of the latch circuit 4 and the output of the 1o frequency divider 12, and sets the mode to the 10 frequency divider 12 only when a phase mismatch occurs a certain number of times in succession. Outputs switching synchronization pulse signal. The 10 frequency divider circuit 12 changes the phase of the signal output to the terminal 13 and the phase synchronization circuit 9 to the timing at which the super frame synchronization pulse signal is output only when the mode switching synchronization pulse signal is output from the phase synchronization circuit 9. change.

FIG. 2 shows the timing of the frame synchronization signal a input to the terminal 5 in FIG. This is an example of a chart showing a case where the set value of the number of consecutive phase mismatches until the phase synchronization circuit 8 outputs the super frame synchronization pulse signal is set to three. In Fig. 2, even if the satellite broadcast radio waves are attenuated and the signal is incorrect as shown in Fig. 2, up to three consecutive errors can be compensated for.
Furthermore, even if the transmitting side changes the synchronization phase as shown in the signal line in FIG. 2, it can be followed instantly. The relationship between the signals in FIG. 2 is from the 9 frequency divider circuit 10 to the 10 frequency divider circuit 1 in FIG.
This is the same as the relationship between the signal input to the phase synchronization circuit 2, the signal input from the latch circuit 4 to the phase synchronization circuit 9, and the output signal of the frequency divider circuit 12.

Effects of the Invention As described above, the present invention can easily stabilize a superframe synchronization signal and a mode switching signal with a simple circuit, and is very effective for stable reception of satellite data broadcasting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronous circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a block diagram of a synchronous circuit in a conventional example. 1...Terminal for bitstream input, 8...
... Phase-locked circuit, 9... Phase-locked circuit,
11...Terminal for outputting super frame synchronization signal, 13...Terminal for outputting mode switching synchronization signal. Name of agent Patent attorney Toshio Nakao and 1 other person 6 -RO Q ++/++J+/ Taste

Claims (1)

[Claims] A circuit that extracts and outputs a super frame synchronization signal and a mode switching synchronization signal from the frame control code portion of an audio bitstream signal output from the BS tuner, and a circuit that divides the frequency of the frame synchronization signal output from the BS tuner by nine. The frequency divider circuit compares the phases of the super frame synchronization signal and the output of the frequency divider circuit, and only when a phase mismatch occurs a set number of times,
a super frame phase synchronization circuit that outputs a super frame synchronization pulse signal to a frequency divider circuit to match the phase of the super frame synchronization signal; a divide-by-10 circuit that divides the output of the divide-by-9 circuit by 10; Comparing the phase of the switching synchronization signal and the output of the 10 frequency divider circuit, and outputting a mode switching synchronous pulse signal to the 10 frequency divider circuit only when a phase mismatch occurs a certain set number of times in succession. A synchronization circuit characterized in that a stable superframe synchronization signal and mode switching output are obtained by providing a mode switching phase synchronization circuit that matches the phase of a mode switching synchronization signal.