JPH0193729U - - Google Patents

Info

Publication number
JPH0193729U
JPH0193729U JP18989387U JP18989387U JPH0193729U JP H0193729 U JPH0193729 U JP H0193729U JP 18989387 U JP18989387 U JP 18989387U JP 18989387 U JP18989387 U JP 18989387U JP H0193729 U JPH0193729 U JP H0193729U
Authority
JP
Japan
Prior art keywords
bonded
semiconductor element
metal film
wiring metal
conductive member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18989387U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18989387U priority Critical patent/JPH0193729U/ja
Publication of JPH0193729U publication Critical patent/JPH0193729U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係る半導体素子の実装構造の
一例を示す断面図、第２図および第３図は本考案
に係る半導体素子の実装順序を例示する斜視図、
第４図は従来の半導体素子の実装構造例を示す断
面図である。 １１……基板、１２……配線金属膜、１３……
半導体素子、１７……外部リード端子、２１……
導電部材、２２……素子搭載部、２５……リード
フレーム。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁体の表面に形成した配線金属膜の所定位置
    に半導体素子を接合する半導体素子の実装構造に
    おいて、一方の端部が前記配線金属膜に接合する
    端子となり、他方の端部が外部リード端子となる
    導電部材を設け、該導電部材の前記所定位置に半
    導体素子を接合し、前記導電部材の前記配線金属
    膜に接合する端子を前記配線金属膜の所定位置に
    接合したことを特徴とする半導体素子の実装構造
    。
JP18989387U 1987-12-16 1987-12-16 Pending JPH0193729U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18989387U JPH0193729U (ja) 1987-12-16 1987-12-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18989387U JPH0193729U (ja) 1987-12-16 1987-12-16

Publications (1)

Publication Number Publication Date
JPH0193729U true JPH0193729U (ja) 1989-06-20

Family

ID=31480901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18989387U Pending JPH0193729U (ja) 1987-12-16 1987-12-16

Country Status (1)

Country Link
JP (1) JPH0193729U (ja)

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